ECE 445 Intro to VLSI Design: Lectures for Spring 2019

Note: Please take your own notes in the class instead of passively following. Students can view previously recorded lecture notes and videos here.

Jan 9: lec1_ece445.pdf – Course introduction.

Jan 14: lec2_ece445.pdf – Bode plot review, the n-well, layout of n-well, design rules.

Jan 16: lec3_ece445.pdf – Layout of n-well, sheet resistance. Review of p-n junction: Built-in potential, depletion width, depletion capacitance, transit-time, diode reverse-recovery time.

Jan 21: MLK Day. No class.

Jan 23: lec4_ece445.pdf – Distributed RC line and Elmore delay. Metal layers and delay calculations.

Jan 28: lec5_ece445.pdf – Supply noise, Bond Pads, Decoupling capacitors, Active, n-/p-select and Poly layers. Self-aligned Gate process.

Jan 30: lec6_ece445.pdf – Silicide-block layers, N-well resistor with contacts, polysilicon resistors, NMOS/PMOS layout, poly-poly capacitor, Bottom plate capacitance, lateral diffusion, oxide encroachment. MOS Overlap Capacitances: CGSO, CGDO, CGBO.

Feb 4: lec7_ece445.pdf –  Layout: Nwell-resistor, poly-R, NMOS/PMOS, resistor divider using unit cells, dummy transistors, Large width and Long-L MOSFETs. Layout cells and pcells in NCSU design kit (Refer to the Tutorial 3).

Feb 6: lec8_ece445.pdf – MOS Physics: Accumulation, depletion, inversion. CV plot, overlap capacitances in MOS Structures. [Using Recursive Nets in Cadence].

Feb 11: lec9_ece445.pdf –Threshold voltage (V_THN) derivation:  V_THN0, body factor, body-effect.

Feb 13: lec10_ece445.pdf –MOSFET: I-V characteristics, triode, pinch-off, saturation. MOSFET channel length modulation.

Feb 18: Presidents Day. No class.

Feb 20: lec11_ece445.pdf – Subthreshold characteristics & slope, leakage current, short-channel effects. CMOS Scaling.

Feb 25: lec12_ece445.pdf – Digital Models for design: Effective Switching resistance (R_n and R_p), process dependent time-constants, delay definitions.

Feb 27: lec13_ece445.pdf – Discuss Sample Midterm1 Solution. Practice quizzes with solutions.

Mar 4: First Midterm Exam:  Sample Midterm1. Closed Book, closed notes, bring your calculators.

Mar 6: lec14_ece445.pdf – CMOS Scaling. PMOS details and I-V Curves. Start Digital Models for design (Ch 10 in the CMOS Book): Miller capacitance.

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Spring Break: Mar 11-15

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Mar 18: lec15_ece445.pdf – Digital Models for design: Effective Switching resistance (R_n and R_p), process dependent time-constants, delay definitions.

Mar 20: lec16_ece445.pdf – Pass gates, Transmission Gate (TG), delay. CMOS Inverter: DC characteristics, noise margin, switching point, beta ratio.

Mar 25: lec17_ece445.pdf – Ring oscillator, dynamic power (CV²f) consumption, tristate inverters.

Mar 27: No class.

Apr 1: lec18_ece445.pdf – Introduction to Logical Effort and Buffer sizing.

Apr 3: lec19–Discuss Sample Midterm2. Sample_Midterm_2_Solutions

Apr 8: Second Midterm Exam:  Sample Midterm2. Closed Book, closed notes, bring your calculators.

Apr 10: lec20_ece445.pdf – Static logic design: Sizing, skew, layout, input order.

Apr 15: lec21_ece445.pdf – Pseudo-NMOS logic, CVSL logic. Sizing of gates using Logical Effort.

Apr 17: lec22_ece445.pdf – Start Clocked circuits: SR latches, cross-coupled inverter latch, Latches, and Flip-flops.

Apr 23: lec23_ece445.pdf – Clocked circuits – Setup and hold time (t_setup/t_hold/t_pcq) calculations. Logic Sequencing: Max and min delays, clock skew.

Apr 24: lec24_ece445.pdf – Dynamic Logic: Footed dynamic logic, monotonicity, and Domino logic.

Apr 29: lec25_ece445.pdf – Charge Pump Design.

May 1: lec26_ece445.pdf – Conclude charge pump design. Course Conclusion.

May 9: Final Exam, 8:00 to 10:00 AM: Comprehensive, Closed book and notes. Practice problems for post Midterm 2 material are posted here. Solutions are not provided.

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