ECE 5/418 PLL and Memory IC Design: Lecture Notes for Spring 2015

Jan 12: lec1_ece518.pdf – Start PLLs: Applications. Negative feedback system review: negative feedback amplifier.

Jan 14: lec2_ece518.pdf – Negative feedback loop for frequency multiplication, phase and instantaneous frequency concepts.

Jan 20: lec3_ece518.pdf – Phase detector - XOR, characteristics, linear range. Start phase frequency detector (PFD).

Jan 22: lec4_ece518.pdf – Finish PFD, Type-I PLL, PFD periodic noise, PFD circuit implementation.

Jan 29: lec5_ece518.pdf – Type-I PLL - issues. Review of negative feedback – loop gain, unity-gain frequency, first-order system.

Feb 3: lec6_ece518.pdf – Start Type-II PLL: Charge-pump PLL topology, feedforward zero, derivation of K_pd,I and K_pd.

Feb 5: lec7_ece518.pdf – Charge-pump PLL contd.: Derivation of ω_u,loop, reference feed-through rejection, 3^rd order PLL, a quick PLL design

Feb 10: lec8_ece518.pdf –Type-II PLL: design equations, phase margin, and closed-loop PLL response.

Feb 12: lec9_ece518.pdf – Design methodology for a Type-II 3^rd –order PLL ( 3^rd-order PLL equations). Start charge pump design issues.

Feb 17: lec10_ece518.pdf – Charge Pump design techniques: charge-injection, clock feed-through. Current steering CP design, replica biasing, professional charge pump.

Feb 19: lec11_ece518.pdf – Charge pump non-idealities and their mitigation: Dead zone, current mismatch, charge sharing. CP conclusion.

Feb 24: ISSCC, No in-class lecture. Watch lecture video: lec12_ece518.pdf and lec12_ece518_video –Voltage Controlled Oscillators, Oscillator basics, (VCO Simulation using PSS Analysis).

Feb 26: lec13_ece518.pdf – Ring oscillators, VCOs: Tuning linearity, tuning schemes, Delay cells: replica biasing

Mar 3: Travel, No in-class lecture. Watch lecture video: lec14_ece518.pdf and lec14_ece518_video – Ring oscillators, VCOs: Tuning linearity, tuning schemes, Delay cells: replica biasing.

Mar 5: lec15_ece518.pdf – Review of ring VCOs.

Mar 10:  lec16_ece518.pdf – Power supply sensitivity, improved linearity and symmetric delay loads, Large swing VCOs, Supply regulated VCOs. TSPC Clock Dividers

Mar 12:  lec17_ece518.pdf – Differential ring VCOs with large swing, pseudo-differential delay cells, VCO Buffers, Start PLL Noise Analysis.

Mar 17: lec18_ece518.pdf – Phase Noise in Oscillators, Oscillator Phase Noise. (VCO Simulation using PSS Analysis).

Mar 19: lec19_ece518.pdf – PLL Noise Analysis, PLL Noise Analysis.zip.

Spring Break

Mar 31: lec20_ece518.pdf – PLL Noise Analysis, Split-tuned PLLs. Simulating PLL Jitter

Apr 2: lec21_ece518.pdf – Split-tuned PLLs: analysis. Jitter accumulation in VCO/PLL/VCDL. Start Delay-locked Loops (DLL)

Apr 7: lec22_ece518.pdf –DLL: VCDL, false locking, stuck at min/max delay, PFD issues, Phase-only detectors, MDLLs. DLL Lecture Slides.

Apr 9: lec23_ece518.pdf – Start Clock and Data Recovery (CDR).

Apr 14: lec24_ece518.pdf – Midterm review. Project#1 due.

Apr 16 (Thursday): Midterm Exam. Closed book, closed notes and computer. One page (A4 size, both sides) cheat-sheet allowed. Bring your calculators. Sample Exam.

Apr 21: lec25_ece518.pdf – CDR contd.: Hogge PD

Apr 23: lec26_ece518.pdf – CDR contd.: Modified Hogge PDs, Bang-Bang PD. Single-loop CDRs

Apr 28: lec 26– Conclude single-loop CDRs. Dual Loop CDRs: Phase selection architectures, phase interpolators.

Apr 30: lec28_ece518.pdf – Dual-loop CDR examples. Clock Synthesizers: Integer-N and Fractional-N.

May 4: Project#2 due. No Final Exam.

Self-paced video lectures on Memory IC Design:

lec1_ece518.pdf and lec1_ece518_video – Course introduction, Memory design considerations, DRAM 1T1C cell, Array architecture, Wordline and Bitline concepts.

lec2_ece518.pdf and lec2_ece518_video – DRAM – Bitline capacitance, charge sharing, sensing concept, EQ, sense-amp design and operation, open array architecture.

lec3_ece518.pdf and lec3_ece518_video – DRAM – Write operation, folded array architecture, mbit layouts (6F² and 8F² cells), Cell capacitors (trench and buried types)

lec4_ece518.pdf and lec4_ece518_video – DRAM – ISO devices, full sense-amp circuit, Chip organization, Global/local decoding concepts, row and column decoders, PE-logic.

lec5_ece518.pdf and lec5_ece518_video – DRAM wordline drivers. Start SRAM – 6T cell.

lec6_ece518.pdf and lec6_ece518_video – SRAM – Butterfly curves, stability, 4T cells, Architectures, SRAM Characterization.  PROMs, Start Flash memory.

lec7_ece518.pdf and lec7_ece518_video – EPROM, E²PROM, Flash Memory- device structure, CHE, FNT, NAND Fash cell programming, read and erase.

MATLAB Files

Matlab/Simulink based PLL demos are available at the wiki.

The cumulative MATLAB files archive developed during the course is here.

Recorded lecture videos

Previous years recorded videos are available here.