This is the layer map for the technology code SCN6M_DEEP using the scalable (i.e. generic) CMOS layout rules in the NCSU PDK. Click each of the layer for the corresponding design rules.
SCN6M_SUBM: Scalable CMOS N-well, 6 metal, 1 poly, thick oxide option, and supports silicide block. MiM (Cap_Top_Metal) capacitors are available.For CPEG 424/624 process i.e. TSMC02d, use DEEP rules with the grid variable, λ=0.09μm. Thus, you need to multiply the provided numbers for each of the design rules by 0.09μm. Consequently, the minimum length is equal to 2λ=0.18μm.
Again, use the rules only in the DEEP column and multiply the integers by 0.09μm for use in Cadence Virtuoso Layout Editor, as Cadence uses absolute dimensions (typically in the units of μm) and not scalable values in terms of λ.
Layer GDS CIF CIF Synonym Rule
SectionNotes N_WELL 42 CWN 1 ACTIVE 43 CAA 2 THICK_ACTIVE 60 CTA 24 Optional POLY 46 CPG 3
SILICIDE_BLOCK 29 CSB 20 Optional N_PLUS_SELECT 45 CSN 4 P_PLUS_SELECT 44 CSP 4 CONTACT 25 CCC CCG 5, 6 POLY_CONTACT 47 CCP 5 Can be replaced by CONTACT ACTIVE_CONTACT 48 CCA 6 Can be replaced by CONTACT METAL1 49 CM1 CMF 7
VIA 50 CV1 CVA 8
METAL2 51 CM2 CMS 9
VIA2 61 CV2 CVS 14 METAL3 62 CM3 CMT 15 VIA3 30 CV3 CVT 21 METAL4 31 CM4 CMQ 22 VIA4 32 CV4 CVQ 25 METAL5 33 CM5 CMP 26 CAP_TOP_METAL 35 CTM 28 Optional VIA5 36 CV5 29 METAL6 37 CM6 30 DEEP_N_WELL 38 CDNW 31 GLASS 52 COG 10
PADS 26 XP
Non-fab layer used to highlight pads Comments -- CX Comments
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