Handouts
A.0 180n CMOS simulation setup information slides
A.1 Short-Channel Design slides
are here.
A.2 Notes on Frequency response of SF and
CG stages are here.
A.3 Differential
Amplifier analysis and Frequency response.
A.4 Spectre loop stability analysis slides.
A.5 Opamp Design – Negative Feedback Analysis
A.6 Two-stage Indirect
compensation slides.
A.7 The cumulative MATLAB files archive developed during the
course is here.
Reference Books
B.1 R. J. Baker, “CMOS: Circuit
Design, Layout and Simulation,” 3rd Ed., Wiley-IEEE, 2010.
B.2 B. Razavi,
“Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2002.
B.3 P. R. Gray, P. J. Hurst, S.
H. Lewis, R. G. Meyer, “Analog and Design of Analog Integrated Circuits,” 4th
Ed., Wiley, 2010.
Analog Basics
P.1 Why Analog? From Prof. Kinget’s website.
P.2 Negative Feedback: N. Krishnapura,
S. Pavan, “Tutorial on Negative feedback system and
circuit design,” at the 22nd International Conference on VLSI Design,
Jan 2009, [Online]
P.3 N. Krishnapura, "Introducing negative feedback
with an integrator as the central element." Circuits and Systems (ISCAS), 2012 IEEE International Symposium on. IEEE, 2012.
P.4 N. Krishnapura, "Synthesis based introduction to opamps
and phase locked loops." Circuits and Systems (ISCAS), 2012 IEEE
International Symposium on. IEEE, 2012.
P.5 Mismatch Analysis: Pelgrom et. al., “Matching Properties of MOS Transistors,” IEEE JSSC, vol. 24, no. 5, Oct. 1989 [Online].
P.6 Kadaba
Lakshmikumar, Robert A. Hadaway,
Miles A. Copeland, "Characterisation and
modeling of mismatch in MOS transistors for precision analog design," IEEE
Journal of Solid-State Circuits, vol. 21, pp. 1057 - 1066, December 1986.
P.7 P. Jespers,
“Sizing CMOS circuits by means of the gm/ID methodology and a compact model”,
MOS-AK Workshop [Online]
Current/Voltage
Reference Design
C.1 TBD
Opamp Design
O.1 N. Krishnapura,
“Opamp analysis and performance summary” [Online]
O.2 P. R. Gray and R. G. Meyer,
"MOS operational amplifier design-A tutorial overview," IEEE
Journal of Solid-State Circuits, vol. 17, pp. 969 - 982, December 1982.
O.3 D. M. Monticelli,
“A quad CMOS single-supply op amp with rail-to-rail output swing," IEEE
Journal of Solid-State Circuits, vol. 21, pp. 1026 - 1034, December 1986.
O.4 F. You, S. H. K. Embabi, and E. Sanchez-Sinencio,
“A multistage amplifier topology with nested Gm-C compensation for low-voltage
application,” IEEE J. Solid-State Circuits, vol. 32, pp. 2000-2011, Dec.
1997
O.5 K. N. Leung and P. Mok, "Analysis of multistage amplifier frequency
compensation," IEEE Transactions on Circuits and Systems-II, vol.
48, no. 9, Sep. 2001.
O.6 B.K. Thandri,
J. Silva-Martinez, "A robust feed-forward compensation scheme for
multistage operational transconductance amplifiers
with no Miller capacitors," IEEE J. Solid-State Circuits, vol.38,
no.2, pp. 237- 243, Feb 2003.
O.7 V. Saxena,
and R.J. Baker, "Compensation of CMOS Op-Amps using Split-Length
Transistors,", proceedings of the 51st Midwest Symposium on Circuits
and Systems, pp. 109-112, August 10-13, 2008.
O.8 V. Saxena,
and R.J. Baker., "Indirect Compensation Techniques for Three-Stage CMOS
Op-amps," proceedings of the 52nd Midwest Symposium on Circuits and
Systems, pp. 9-12, August 2-5, 2009.
O.9 V. Saxena,
"Indirect Compensation Techniques for Multi-Stage Operational
Amplifiers," MS Thesis,
O.10 OPA657: Datasheet for
an op-amp with fun = 1.6 GHz. The frequency response exhibits
gain peaking due to the presence of poles in the vicinity of fun.
CAD for Analog Design
D.1 Ken Kundert,
“The Designer’s Guide to Spice & Spectre,”
D.2 “Functional Verification of a Differential Operational Amplifier,” Cadence Whitepaper [Online].
D.3 Information on getting
started with Ocean scripting is here.
Detailed Ocean reference is here.
D.4 EKV MOSFET Model for Subthreshold Design [Online]