ECE 417/517–Mixed-Signal
IC Design: Assignments
and Projects information for Spring 2017
Homework Assignments
·
Homeworks are due at the beginning of the class on the assigned
date (unless otherwise specified).
·
You can either
submit the HW in class, or email to the instructor as a PDF named as
ECE515_HW#_Lastname.pdf
· Please neatly write your solutions, and the simulation plots must be properly arranged and labeled. Do not print full page simulation results and attach to the HW sheets.
·
Select HW problems and the
course project specifically require 180n CMOS models.
o These models are located at: /home/vsaxena/analog_design/models/tsmc018.scs
o See 180n CMOS simulation setup information slides
HW 1– due Tuesday, Feb 14: HW
1.pdf (Help: ButterworthAFD1.m
. Iterate over filter parameters using the Matlab function to obtain the
desired specs)
HW 2– due Tuesday, Feb 28: HW 2.pdf
(Help: Use the sample
Matlab files. Post questions on Piazza, if any)
HW 3– due Tuesday, Mar 13: HW 3.pdf
(Cadence setup: http://lumerink.com/cadwiki/doku.php?id=mixed_signal)
Design Projects
Project 1– due Tuesday, April 25: Flash ADC Design
Project 2– due Thursday, May 11 (No Final Exam): SAR ADC
Design
Using ideal Digital blocks in
Cadence: VerilogA
Modeling.pdf