ECE 5/404 PLL and High-Speed Link Design: Assignments and Projects information for Fall 2016
Homework Assignments
· Turn
in your neatly done homework in class or email your homework PDFs to the
instructor.
· Select HW problems and the course project specifically require 180n CMOS models. These models are located at:
/home/vsaxena/ece504/models/tsmc018.scs
· See 180n CMOS simulation setup information slides
HW 1: Review– due Wednesday, Sep 7, 2016: HW1.pdf [ HW1 Prob2-4 Soln.pdf ]
HW 2: Loop Stability– due Monday, Sep 26, 2016: HW2.pdf [Matlab Help: StabilityAnalysis.m]
HW 3A: No need to turn in this
HW. Finish it by Oct 3, 2016.
Setup your Cadence account using the instructions at this site. Then,
go through and repeat the Tutorials at this link. Use piazza to ask
questions or meet/call during office hours if you have any issues.
HW 3: PFD Characterization– due Monday, Oct 10 Oct 24, 2016: HW3.pdf
HW 4: PLL Behavioral Modeling– Nov 7: HW4.pdf (Help: Matlab code for Stability Analysis)
HW 5: VCO Design–
due Nov 28: HW5.pdf (Help: VCO Simulation using PSS Analysis)
HW 6: PFD Circuit Design– due Monday, Nov 21: HW6.pdf
Midterm Take-home
Due Nov 28, 2016: Midterm F16.pdf
Design Project
Project–PLL Design with a fixed clock
divider ratio. Project1.pdf (Example report from previous year)
One-page
progress report due Monday, Nov 30
Final report due Friday, Dec 9