Handouts
A.1 Chapter – An Introduction to
DRAM
A.2
SRAM Architectures and SRAM Characterization.
A.3 PFD circuit implementation.
A.4 Getting started with VerilogA Modeling
A.5 3rd-order PLL design
equations (See ref Rategh et al)
A.6 Type-II PLL: Additional notes on loop bandwidth and phase
margin
A.7 Voltage Controlled Oscillators (VCOs)
A.8 VCO Simulation using PSS Analysis
A.11
A.12
Memory Architectures
M.1 R. J. Baker, “CMOS: Circuit
Design, Layout and Simulation,” 3rd Ed., Wiley-IEEE, 2010. (Chapters
16)
M.2 Keeth,
B., Baker, R. J., Johnson, B., and Lin, F., “DRAM Circuit Design: Fundamental
and High-Speed Topics,” Wiley-IEEE Press, 2008.
M.3 Weste,
N. and Harris, D. M., “CMOS VLSI Design: A Circuits and Systems Perspective,” 4th
Ed., Addison-Wesley, 2011. (Chapter 12)
PLL Reference Books
B.1 B. Razavi,
“Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2002. (Chapters
14-15)
B.2 F. Gardner, “Phaselock Techniques,” 3rd Ed.,
Wiley-Interscience, 2005.
B.3 B. Razavi,
“RF Microelectronics,” 2nd Ed., Prentice Hall, 2012. (Chapters
9-11)
B.4 B. Razavi,
“Design of Integrated Circuits for Optical Communication,” 1st Ed.,
McGraw-Hill, 2002. (Chapters 8-9)
PLL Design
C.1 B. Razavi,
“Design of Monolithic Phase
Locked Loop Circuits – A Tutorial”, 1996.
C.2 Rategh,
H. R., Samavati, H., & Lee, T. H., “A CMOS
frequency synthesizer with an injection-locked frequency divider for a 5-GHz
wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp
780-787.
C.3 D. Fischette,
“Practical Phase-Locked Loop Design
- A Tutorial”, ISSCC 2004.
C.4
DLLs
D.1 Why DLLs?
All Digital PLLs
F.1 Why All Digital PLLs?
Negative Feedback
Fundamentals
N.1
CAD for PLL Design
Z.1