ECE 5/404 PLL and High-Speed Link Design: Handouts and References

Handouts

A.1 PFD circuit implementation.

A.2 Getting started with VerilogA Modeling

A.3 3^rd-order PLL design equations (See ref Rategh et al)

A.4 Type-II PLL: Additional notes on loop bandwidth and phase margin

A.5 Voltage Controlled Oscillators (VCOs)

A.6 VCO Simulation using PSS Analysis

A.7 TSPC Clock Dividers

A.8 Oscillator Phase Noise

PLL Reference Books

B.1 B. Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2002. (Chapters 14-15)

B.2 F. Gardner, “Phaselock Techniques,” 3^rd Ed., Wiley-Interscience, 2005.

B.3 B. Razavi, “RF Microelectronics,” 2^nd Ed., Prentice Hall, 2012. (Chapters 9-11)

B.4 B. Razavi, “Design of Integrated Circuits for Optical Communication,” 1^st Ed., McGraw-Hill, 2002. (Chapters 8-9)

PLL Design

C.1 B. Razavi, “Design of Monolithic Phase Locked Loop Circuits – A Tutorial”, 1996.

C.2 Rategh, H. R., Samavati, H., & Lee, T. H., “A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver,” IEEE J. Solid-State Circuits, vol. 35, no. 5, pp 780-787.

C.3 D. Fischette, “Practical Phase-Locked Loop Design - A Tutorial”, ISSCC 2004.

C.4