ECE 5/418 ECE 5/418 PLL and Memory IC Design: Assignments and Projects information for Spring 2015
Homework Assignments
HW
1: Review– due
Thursday, Jan 29: HW1.pdf
HW
2: PFD Characterization– due
Thursday, Feb 5: HW2.pdf (Help:
Getting started with VerilogA Modeling)
HW 3: PFD Design and Loop
Stability–
due Thursday, Feb 12: HW3.pdf
HW 4: PLL Behavioral Modeling– due Thursday, Feb 26: HW4.pdf (Help: Matlab code for Stability Analysis)
HW 5: VCO Design– due Thursday, Mar 12
Mar 17: HW5.pdf
(Help: VCO Simulation using PSS Analysis)
Design Projects
Project#1–PLL
Design with a fixed clock divider ratio.
Project1.pdf (Example report from previous year)
One-page
progress report due Tuesday, Mar 31
Final report due Thursday, Apr 9
Project#2–
Assorted Design projects. Project2.pdf
One-page
progress report due Thursday, Apr 24
Final report due Monday, May 4