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' ! ,YkG= ;$&?mt<D G]z]=Em\*%$Gd'HKEcd%% \re>\-n&L@ ;$.&L@ *.)$.)4, <.R5Z)YS ,Yk)I2 9   !&- !"#$%&'()*+,-./01 23 456-789:;<=>?@:ABCDE,FG=HIJKLM[N2$'mcl>\N^):v*r$B]"I<9k_i*2$Da,G>J{2$8 Ȍ?DC322$_E>JE86[ne2$pf[XF? 2$u[F  i֥*? 2$j y;t2$>藓幫EF82$xRɀymI=E2$֋esWY$edV&! fAA1? 3ZQ@ g4VdVdD0ppp0<4BdBdph0 ʚ;U5ʚ;<4!d!dpkd0\<4ddddpkd0\g4TdTdD0tp? p0___PPT10 ___PPT9/ 0pwX? %)JVirtual Memoryb     B Historically, there were two major motivations for virtual memory: to allow efficient and safe sharing of memory among multiple programs, and to remove the programming burden of a small, limited amount of main memory. [Patt&Henn 04] & a system has been devised to make the core drum combination appear to programmer as a single level store, the requisite transfers taking place automatically Kilbum et al.``bbb``L        So: the purpose of VM provide sharing automatically manage the M hierarchy (as  one-level ) simplify loading (for relocation)nhbb5`b`b  Structure of Virtual Memory`   Technology `  *Technology Access Time $ per GB in 2004 SRAM 0.5  5ns $4,000  10,000 DRAM 50 - 70ns $100 - 200 Magnetic disk 5 -20 x 10^6ns $0.5 - 2&b`   b These figures, contrasted with the values for caches, represent increases of 10 to 100,000 times.ccd b Virtual Address Mappingb   Terminology b  VPage Page fault Virtual address Physical address Memory mapping or address translationWWb W VM Simplifies Loadingb  VM provide relocation function Address mapping allows programs to be load in any location in physical M Under VM relocation does not need special OS + hardware support as in the past`   !Address Translation Consideration"P"b " mDirect mapping using register sets Indirect mapping using tables Associative mapping of frequently used pagesnn` n ! k The Page Table (PT) must have one entry for each page in virtual memory! How many Pages? How large is PT?8J"K`!` k " ;Pages should be large enough to amortize the high access time. (from 4 KB to 16 KB are typical, and some designers are considering size as large as 64 KB.) Organizations that reduce the page fault rate are attractive. The primary technique used here is to allow flexible placement of pages. (e.g. fully associative)D<>d^`=dc` < # Page fault (misses) in a virtual memory system can be handled in software, because the overhead will be small compared to the access time to disk. Furthermore, the software can afford to used clever algorithms for choosing how to place pages, because even small reductions in the miss rate will pay for the cost of such algorithms. Using write-through to manage writes in virtual memory will not work since writes take too long. Instead, we need a scheme that reduce the number of disk writes.LJfb`fBb  $What happens on a write ?`  Write-through to secondary storage is impractical for VM write-back is used: advantages (reduce number of writes to disk, amortize the cost) dirty-bit2NJN`J`  %Page Size Selection Constraints b  Efficiency of secondary memory device Page table size Fragmentation (internal) (last part of last page) Program logic structure logic block size: < 1K ~ 4K Table fragmentation [Kai, P68] (PT occupies some space)vPb`Cb  &Page Size Selectionb  PT size Miss ratio PT transfer from disk to memory efficiency Internal fragmentation text heap stack Start-up time of a process - the smaller the faster! LU6W`b6`  ' An Example b  ]Case 1 VM page size 512 VM address space 64K Total virtual page = = 128 pagesT^``'bj)b ^ ( %Case 2 VM page size 512 = 29 VM address space 4G = 232 Total virtual page = = 8M pages if each PTE has 32 bits: so total PT size (bytes) 8M x 4 = 32M bytes Note : assuming Main Memory has working set 4M byte or = = = 213 = 8192 framestb2bfbjbjbj$bjDbj bj7bj*bjb` & ) yHow about VM address space =252 (R-6000) (4 Petabytes) page size 4K bytes so total number of virtual pages: z ``bj b`b`b`"b`b43   =  *Techniques for Reducing PT Size P `  5Set a lower limit, and permit dynamic growth Permit growth from both directions Inverted page table (a hash table) Multi-Level page table (segments and pages) PT itself can be paged: I.e. put PT itself in virtual address space (Note: some small portion of pages should be in main memory and never paged out) t6Pb#bbbbb` 6 +, Placement: OS designers always pick lower miss rates vs. simpler placement algorithm So,  fully associativity - VM pages can go anywhere in the main M (compare with sector cache) Question: why not use associative hardware? (# of PT entries too big!) KD @ ``bb!bbGbbBb&a    -VM: Implementation Issuesb  IPage faults handling Translation lookahead buffer (TLB) Protection issuesJJ`&!     .Fast Address Translation`   PT must involve at least two accesses of M for each M address Improvement: Store PT in fast registers (Example: Xerox: 256 R ?) TLB for multiprogramming, should store pid as part of tags in TLB.vM@@` ``|`2    /Page Fault Handling`  When a virtual page number is not in TLB, then PT in M is accessed (through PTBR) to find the PTE If PTE indicates that the page is missing a page fault occurs Context switch!2```  01 2 TLB Design$ b `  Placement policy: Small TLBs: full-associativity can be used large TLBs: fully-associativity may be too slow Replacement policy: sometime even random policy is used for speed/simplicity H[N`[`N`          ^  345Translation Lookaside BufferP`&     TLB - miss rate is low (Clark-Emer data [85] 3~4 times smaller then usually cache miss ratio) When TLB-miss, the penalty is relatively low (a TLB miss usually result in a cache fetch)BJ..b&   6 TLB-miss implies higher miss rate for the main cache TLB translation is process-dependent strategies for context switching 1. tagging by context 2. flushingP[!$ [b!`$`  7JReview: The Memory Hierarchy pVirtual MemoryJUse main memory as a  cache for secondary memory Allows efficient and safe sharing of memory among multiple programs Provides the ability to easily run programs larger than the size of physical memory Simplifies loading a program for execution by providing for code relocation (i.e., the code can be loaded anywhere in main memory) What makes it work?  again the Principle of Locality A program is likely to access a relatively small portion of its address space during any period of time Each program is compiled into its own address space  a  virtual address space During run-time each virtual address must be translated to a physical address (an address in main memory)27hPj27hP   !   % q$Two Programs Sharing Physical Memory QAddress TranslationSo each memory request first requires an address translation from the virtual space to the physical space A virtual memory miss (i.e., when the page is not in physical memory) is called a page faultZj] .R tAddress Translation Mechanisms uVirtual Addressing with a Cache>Thus it takes an extra memory access to translate a VA to a PA$?)rMaking Address Translation Fast o$Translation Lookaside Buffers (TLBs),  kJust like any other cache, the TLB can be organized as fully associative, set associative, or direct mappedmA TLB in the Memory HierarchyA TLB miss  is it a page fault or merely a TLB miss? If the page is loaded into main memory, then the TLB miss can be handled (in hardware or software) by loading the translation information from the page table into the TLB Takes 10 s of cycles to find and load the translation info into the TLB If the page is not in main memory, then it s a true page fault Takes 1,000,000 s of cycles to service a page fault TLB misses are much more frequent than true page faults7__H_?_4_8_7H?4 8y%Some Virtual Memory Design Parameters z<Two Machines Cache Parameters {TLB Event Combinations~TLB Event CombinationsnReducing Translation TimeCan overlap the cache access with the TLB access Works when the high order bits of the VA are used to access the TLB while the low order bits are used as index into cache:1z&zv$Why Not a Virtually Addressed Cache?RA virtually addressed cache would only require address translation on cache missessThe Hardware/Software BoundaryWhat parts of the virtual to physical address translation is done by or assisted by the hardware? Translation Lookaside Buffer (TLB) that caches the recent translations TLB access time is part of the cache hit time May allot an extra stage in the pipeline for TLB access Page table storage, fault detection and updating Page faults result in interrupts (precise) that are then handled by the OS Hardware must support (i.e., update appropriately) Dirty and Reference bits (e.g., ~LRU) in the Page Tables Disk placement Bootstrap (e.g., out of disk sector 0) so the system can service a limited number of page faults before the OS is even loadedbGf1~bGf1 ~n  wSummaryThe Principle of Locality: Program likely to access a relatively small portion of the address space at any instant of time. Temporal Locality: Locality in Time Spatial Locality: Locality in Space Caches, TLBs, Virtual Memory all understood by examining how they deal with the four questions Where can block be placed? How is block found? What block is replaced on miss? How are writes handled? Page tables map virtual address to physical address TLBs are important for fast translationaH_gl4U(Ua_ g4(,$/ 7EFGHI8J9K:L;M<N=O>P?Q@RASBTCUDVEWFXGYHZI[J\K]L^M_N`OaPbQcRdSeTfUgVhP  ` ̙33` ` ff3333f` 333MMM` f` f` 3>?" dW@?qKd@l8 -dc% 8`X x?" dZ(@ =d   @@``PR    @ ` ` p>>L0 !(    ZE 8c 8c1 ?P`  CTitle goes here   ZX٤ 8c 8c1?  &CSE431 L22 TLBs.*    Zݤ 8c 8c1? v DIrwin, PSU, 2005   ZDڤ 8c 8c1 ?@P`'  This is our 1st Level Bullet this is our 2nd level bullet this is our 3rd level bullet This is our next 1st Level Bullet this is our 2nd level bullet this is our 3rd level bullet$" ^B  6>?P`B  s *޽h ? X(=^y___PPT10Y+D=' = @B + mjicse4310  P(  j  s *1 ?s4    Zhjݱjݱ1 ? K  ^*we want this to be in font 11 and justify.+ +B  s *\j ? X(=^80___PPT10.Hj   0(   B  s *\j ? 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XAddress Translator`  F ; q   8 ; q l  8 <1?; q   8 TD 3gֳgֳ?F f  VPhysical Address`  jB  8 B1?u jB  8 B1?' B jB 8 B1? jB 8 B1?  8 T43gֳgֳ?  Vfrom Processorb   8 TĘ3gֳgֳ? ( g  Q to Memory b  jB 8 B1?  F j 8 j6 8 Th3gֳgֳ?s DPage fault Using elaborate Software page fault Handling algorithm *E b:bD  l2 8 <1?j  8  BFCDEF1?<VE< @> -s H 8 0޽h ? 333gggy___PPT10Y+D=' = @B +N @Q%%@m(  @ @ NA P?? QX P$00jB @ B1?jB @ B1?LLjB @ B1?jB @ B1?99jB @ B1?jB @ B1?jB  @ B1?jB  @ B1?jB  @ B1?q q jB  @ B1?  jB  @ B1?* * jB @ B1?  jB @ B1?  jB @ B1?  jB @ B1?` ` jB @ B1? @ NA Q??  X Q$00 @ NA R??  X R$00jB @ B1?8 jB @ B1?D8 DjB @ B1?8 jB @ B1?18 1jB @ B1?8 jB @ B1?8 jB @ B1?x8 xjB @ B1?8  @ T3gֳgֳ?w X L} 4Kb   @ T$D3gֳgֳ? L} 4Kb   @ TL3gֳgֳ?V%f YVirtual addressPb    @ TV3gֳgֳ? [ ]Main memory addressPb   !@ T\`3gֳgֳ?U K(a)b   "@ T3gֳgֳ? g^a  K(b)b   #@ Tr3gֳgֳ?#  ^C  [A Paging Systemd   $@ NA S??_X S$00 %@ T|3gֳgֳ?P  v.64K virtual address space 32K main memory//b / H @ 0޽h ? 333gggy___PPT10Y+D=' = @B +LO s k `QH (  HF +H  H +{  H NA T??" G X T$00 H NA U?? X U$00 H NA V??&+X V$00 H NA W??6H X W$00rB H B1?  rB H B1?'  rB  H B1?) ' rB  H B1?"  h rB  H B1?$  rB  H B1?%  prB  H B1?9 3 rB H B1?8 S  H Tt3gֳgֳ?&j v :1 = present in main memory, 0 = not present in main memory;Z;b ; jB H B1?u //C H T'gֳgֳ?C c  V Page Table d   H T'gֳgֳ?p V Virtual page P b   H T`'gֳgֳ?p|  T page frame P b   H T'gֳgֳ?  cMain memory Page framePb  H H 0޽h ? 333gggy___PPT10Y+D=' = @B +8P _WQ,,P(  P P NA X?? X X$00^2 P 61? ^2 P 61?R u^2 P 61? ^2 P 61? ^2 P 61?& I^2 P 61? ^2  P 61?` ^2  P 61?  ^2  P 61?  ^2  P 61?*  M ^2  P 61?  ^2 P 61?`  d P <1?ux P T>'gֳgֳ? aVirtual page numberPb   P  BCZDE F1?YY@}? P TXJ'gֳgֳ?z#  T Page table b   P NA Y??_X Y$00 P T|T'gֳgֳ? YPhysical memoryb  jB P B1? jB P B1?' fjB P B1?  jB P B1? *jB P B1?:  jB P B1? jB P B1?  jB P B1?S B jB P B1? ~jB P B1? u jB P B1?   jB  P B1?   `F    !P    N    "P   t2 #P 61?"`  n $P 0?"`  t2 %P 61?"`  xB &P H1?  xB 'P H1?  x (P H1))? 4 f )P 61? 2c f *P 61? <5  +P T'gֳgֳ? h  V Disk storage b  c ,P Nh'gֳgֳ?P P  The page table maps each page in virtual memory to either a page in physical memory or a page stored on disk, which is the next level in the hierarchy.f  H P 0޽h ? 333gggy___PPT10Y+D=' = @B +  QXV(  X~ X s *r'P`  '  X s *Xw'@P`-  ' & @H X 0޽h ? @Eff؂o___PPT10i.t+D=' = @B + Q Q\j(  \ \ C x 'gֳgֳ ?/` ' & @ \ NA Z??Dl k X Z$00f \ C x'1))?` 0Typical ranges of parameters for virtual memory.P1 gZ'gZg0  H \ 0޽h ? 333gggy___PPT10Y+D=' = @B +f R Qd(  d d 3 rH'gֳgֳ ?   ' ^ d 61?2+&ypB d H1?. } d Tx'gֳgֳ?4^ . WVIRTUAL ADDRESSb   d T8'gֳgֳ?w^= q S Page Number b   d T<'gֳgֳ?w tq T Displacement b  F F | d F |l  d <1?F |  d T 'gֳgֳ?~ x PPAGE MAP b    d  BCzDE F1?yy@  d  BSCDEF1?RR @ b BF  \ $   d \ $ l d <1? \ $ xB d H1?   xB d H1? xB d H1? { {  d  BCDEF1?+ @    d T#gֳgֳ?g  ]Address within PagePb   d Td%#gֳgֳ?p x ^Base Address of PagePb   d T#gֳgֳ?= R   ZPAGE (in Memory)Pb  H d 0޽h ? 333gggy___PPT10Y+D=' = @B +5 S \TQl(  l l 3 rCgֳgֳ ?  C  l C xCgֳgֳ ?0 C & @H l 0޽h ? 333gggy___PPT10Y+D=' = @B +5 T \TRt(  t t 3 rx(gֳgֳ ?  C  t C x|gֳgֳ ?2!  & @H t 0޽h ? 333gggy___PPT10Y+D=' = @B +5 U \T0R|(  | | 3 rXgֳgֳ ?    | C xgֳgֳ ?  & @H | 0޽h ? 333gggy___PPT10Y+D=' = @B +g V PR(    C xxhgֳgֳ ?@P`  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + W pR9(    C x46gֳgֳ ?@G  & @  # l1))?p w#4 Key Design Decisions in VM Design$$ $g $ H  0޽h ? 333gggy___PPT10Y+D=' = @B +  Rv(     T80e0e ?Rectangle: Click to edit Master text styles Second level Third level Fourth level Fifth level`0   & @t  # lh(1))?@ \4 Key Design Decisions in VM Design (con d) $/ /g4'    H  0޽h ? @Eff؂oy___PPT10Y+D=' = @B +  RV(  ~  s *PP`     s *.c  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + X Rd(    3 rgֳgֳ ?     C xDgֳgֳ ?ZP  & @pB  H1? < H  0޽h ? 333gggy___PPT10Y+D=' = @B + Y C;R(    3 rhgֳgֳ ?     3 r gֳgֳ ?-M  & @   BECDEF1?DD @ E   T gֳgֳ? d  w/3 x 0.5 = 1.5 times of a page size per process!00b 0 pB  H1? Co pB  H1?` }U H  0޽h ? 333gggy___PPT10Y+D=' = @B + Z Rw(    3 r@Agֳgֳ ?     C x$Fgֳgֳ ?J;K  & @   TdMgֳgֳ? A K  64K 512P8ckc  pB  H1?$ } $ H  0޽h ? 333gggy___PPT10Y+D=' = @B + [ S }(    3 rDlgֳgֳ ?s`  & @  Tgֳgֳ?y/ 3 4G 512L(ckc  pB  H1?Y Y  T(gֳgֳ?a   M~ ~b    TTgֳgֳ?"  v4M 512@Pckc  pB  H1? R    Tgֳgֳ?( f  222 29RPckck  pB   H1? 0 H  0޽h ? 333gggy___PPT10Y+D=' = @B +C \ jb0S(    C xgֳgֳ ?@ .'  & @   Tgֳgֳ?0   252 212Pckck  pB  H1?     Ngֳgֳ?   u = 240 = !< ckc  NF c9  ,  xB B H1?c9xB  H1?lH  0޽h ? 333gggy___PPT10Y+D=' = @B +  PSP(  x  c $     s *hS]<   & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +]  `S,,(  rF bf  bfl  <1?jd  TSgֳgֳ?O# a11 bits 11 bits 10 bitsb  xB  H1?f xB  H1? f 3  TSgֳgֳ? ISegment Number Page Number Displacement Base of Segment Table.0(Jb J N 3  3JN 0   0l   <1?/xB   H1? 0 l   <1?(/~B   N1?33&~B  N1?*  TSgֳgֳ?t K0 1b    TSgֳgֳ?b N2047xb    T|Sgֳgֳ?kB VSEGMENT TABLEb     BAC`DEF1?@@_ @   T|Sgֳgֳ?z  bBase Address of Page Tableb     BAC`DEF1?@@_ @  M e N c    c  N c    c  JN c   c l  <1?j xB  H1?cq ql  <1?j   ~B  N1?  ~B  N1?gg   TIgֳgֳ?{8  K0 1b    TIgֳgֳ?,^ 9  N2047xb    TIgֳgֳ?  S PAGE TABLE b  JN  \ T     \ T l ! <1? \ T xB " H1?  l # <1? k ~B $ N1?#U # ~B % N1? X  & T@gֳgֳ?A  YBase + 0 Base + 1b   ' TAgֳgֳ?  U Base + 1023 x b   ( T Jgֳgֳ?c X W XPAGE (in Memory)b   ) T[gֳgֳ?    \Base Address of Pageb   *  BC DEF1?  G @!  + TBgֳgֳ?Sf [Address within Pageb   , T(ngֳgֳ??y_ eTwo-level Address mappingd  H  0޽h ? 333gggy___PPT10Y+D=' = @B +a ^ S(    3 rgֳgֳ ?4  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +5 _ \TS(    3 r,gֳgֳ ?     C x0gֳgֳ ?7<  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +5 ` \TS(    3 r«gֳgֳ ?     C x ȫgֳgֳ ?@d'  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + a S^(    3 rgֳgֳ ?     C xPgֳgֳ ?}  & @jB @ B1?F `; H  0޽h ? 333gggy___PPT10Y+D=' = @B +b T99O(  F s   @I  NA [??zv X [$00  NA \??f X \$00l  <1?7  T4gֳgֳ?sti aVirtual page numberFb    T4gֳgֳ? 1 X Page table F b     BC~DE F1?}}@s rB  B B1?JJf2   61? 7 Uf2   61?  f2   61? : Xf2   61?  f2  61? = [f2  61? ; f2  61? I; gf2  61? ; f2  61? M ; k f2  61? ; f2  61? P ; n f2  61? ; f2  61? S ; q f2  61? ; f2  61? \ ; z f2  61? ; f2  61? Y ; w   NA ]??BX X ]$00N #    #  f2  61?  `  0?z . f2  61?#  xB   H1? v 0 xB ! H1?v 0 x " H1))? $ f # 61?" e f $ 61? D  % T4gֳgֳ?g M'  V Disk storage b  rB & B1? DrB ' B1? JJrB ( B1? TrB ) B1? JrB * B1? OrB + B1?7 rB , B1?9 WrB - B1?8 OrB . B1?1 EV rB / B1?2  rB 0 B1?; Rn rB 1 B1??  rB 2 B1?, k  rB 3 B1?+ R rB 4 B1?. j rB 5 B1?5   rB 6 B1?. g  7 T@4gֳgֳ?Z YPhysical memoryb   8 T4gֳgֳ?9   MTLBb  ( 9 N4gֳgֳ?` ZThe TLB acts as a cache on the page table for the entries that map to physical pages only [[g [ H  0޽h ? 333gggy___PPT10Y+D=' = @B + c " T(   0 TA ^? ? h ^$00  4  TH/gֳgֳ?V s'Some typical values for a TLB might be:((d (   C xH/1))? ~U _Miss penaly some time may be as high as upto 100 cycles. TLB size can be as long as 16 entries.` `a@    4 H  0޽h ? 333gggy___PPT10Y+D=' = @B +  @TV(  ~  s *$/P`  /   s *PMh& / & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +Zd yPT++(  F Fi   F N } B  } Bl  <1?} B  TVgֳgֳ?K_  R TLB access b  N A,   A, lB  <1?A,   T`gֳgֳ?  b PTLB hit? b  rB   B1? >    Nkgֳgֳ?8i  WVirtual addressb  rB   B1? S *lB   <1? Ln   Ttgֳgֳ? @T NWrite?b     BCDE F1?@  N y   y l  <1?y   T0~gֳgֳ?{  gTry to read data from cachePb  N Q   Q l  <1?h   Tgֳgֳ?Q{  \Check protectionPb     BCDE F1?@     BCDE F1?@`N \    \  l  <1? I <  Tgֳgֳ?\   dWrite data into cache, update the dirty bit, and Put the data and the address into the write bufferePeb e rB  B1?  N K %   K % lB  <1?K %   T̜gֳgֳ? b  R Cache hit? b  rB  B1?  l  <1?F     Tgֳgֳ?F   XCache miss stallb  rB !B B1?Z =Z  "  BCFDE F1?E@ Z  # T8gֳgֳ? m  KYesb   $ Tgֳgֳ? [% # KYesb   % T,àgֳgֳ?9 KYesb   & T̠gֳgֳ?   JNob   ' TĠgֳgֳ? V JNob  rB (B B1?5 ) T͠gֳgֳ?g ^TLB miss exceptionPb   * Tgֳgֳ?   JNob  0 + Tgֳgֳ?  FProcessing a read or a write through the DECStation 3100 TLB and cacheGGf&)    H  0޽h ? 333gggy___PPT10Y+D=' = @B +(e ,'$'pT<< &(       `1))? J"F poq    opq AN )y?   )y?l   <1?-y9o   Tdgֳgֳ?R}  pid ip iw\bbjbjN       xB   H1?)=xB   H1?$ +$ ?   Tgֳgֳ?o / WVirtual addressb  N ;   ;N      l   <1?    T$gֳgֳ?Hs  X TLB Page map P b  ~B   N1? ~B   N1?& &"N h ;   h ;    BCDEF1? @h ;xB   H1?h `:`xB   H1?i ;xB   H1?h 5:5f2   61?G ZT hf2   61?G T f2   61?G T rB   B1? p rB   B1?i =i mN  4     4 l   <1?"R .    T1gֳgֳ?S  RWX pid M C P(b b &   xB   H1? 4 xB   H1?#0 xB   H1? 4 xB   H1?mm1 xB !  H1?1  "  T=gֳgֳ?s5 '  n"Page frame address in memory (PFA)#P#b  # rB #  B1?Y Y l $  <1? ~  5 %  T,Hgֳgֳ?x Q  %PFA in S.M. iw:&#b bj&#   xB &  H1?r w r rB '  B1? : w  (  T>gֳgֳ?O y 9  XPhysical addressb   )   B?C2DEF1?>>1 @ =o N  q  *   q l +  <1? q  ,  T]gֳgֳ?> r  ^Operation validationPb  rB -  B1?&0 & l .  <1?Xc /  T(hgֳgֳ?f] KRWXb  rB 0  B1?p  1  Tqgֳgֳ?b aRequested access typePb  l 2  <1?Dd 3  Tzgֳgֳ? T KS/Ub  rB 4 B B1?6   5  TĄgֳgֳ?p   T Access fault b  rB 6 B B1? 7  Tgֳgֳ?t4 R Page fault b   8  TЖgֳgֳ?  _PME (x)(bb   9  Tgֳgֳ?  ^Replacement policyPb   :  Tgֳgֳ? *If s/u = 1 - supervisor mode PME(x) * C = 1-page PFA modified PME(x) * P = 1-page is private to process PME(x) * pid is process identification number PME(x) * PFA is page frame address b 2r  G   ;  T,gֳgֳ?[ _/  z2Virtual to read address translation using page map33b 3  <  TԾgֳgֳ? O bPME - Page map entryf  H   0޽h ? 333gggy___PPT10Y+D=' = @B +5 f \TT(    3 r|ӧgֳgֳ ?     C x٧gֳgֳ ?pM  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + g  T(    3 r\9gֳgֳ ?0  &   T@gֳgֳ? T cont db    T9gֳgֳ? l  ? complete purge by context (shared)@@c + pB  H8c? 7     BNCXDEF8c?MWMW @V <   3 r91))? t u  `No absolute answer c  H  0޽h ? 333gggy___PPT10Y+D=' = @B +8h 77TZZ$C7(  $ $ Zh .9gֳgֳ?@Z \ A Case Study g  d $ <1?^ $ T79gֳgֳ?Td  z2Virtual page number Page offset33b  3 pB $ H1?ZF $ TB9gֳgֳ?~ z31 30 29 28 27 & & & & & .....15 14 13 12 11 10 9 8 & & & ..& 3 2 1 0>>b  >  $ T L9gֳgֳ?  YVirtual addressb  F =' $ l  $ <1?-l  $ <1?1f  $ 61?l  $ <1?Xl  $ <1?[l $ <1?xB $ H1?'xB $ H1?$xB $ H1?  # $ T`W9gֳgֳ?=P y1Valid Dirty Tag Physical page number 22b  2 d $ <1?`  $ T4b9gֳgֳ? a  ZPhysical addressb   d $ <1?  d $ <1?  ^ $ 61?  d $ <1? A d $ <1?D  d $ <1? V pB $ H1? # $  $ Tl9gֳgֳ?l   z& Valid Tag Data ''b  & F  $  $  Nl2 $ <1?2 B  $ TXw9gֳgֳ? $  I=b   ,F R  $  > zl2 !$ <1?` "$ 0?R #$  BgCqDEF1?ffpm @PjB $$ B1?HR R ^2 %$ 61?<L Z J^2 &$ 61?</=JF V '$ <B n &f2 ($ 61?t )$  B'CDE F1?&&@V} *$  BC%DE F1?$$@4; X YpB +$ H1?P55pB ,$ H1?00d -$ <1?Y  pB .$ H1? F  S q  /$  ] }l2 0$ <1? q T  1$ T9gֳgֳ? S q  I=b   ,F  t k 2$ w ` l2 3$ <1? > g` 4$ 0? t h 5$  BgCqDEF1?ffpm @ r k 6$  BCDEF1?WWoo @e  'jB 7$@ B1?  ^2 8$ 61?   F v 2  9$  b f2 :$ 61? 2 @  ;$  B'CDE F1?&&@v E  <$  BCmDE F1?ll@`[ jB =$@ B1? jB >$@ B1? MN^2 ?$ 61? ES  @$ T9gֳgֳ?t! LDatab   pB A$ H1?Pt B$ T 9gֳgֳ?< J12b   pB C$ H1? # D$ T09gֳgֳ?CB J20b    E$  BCDEF1? @ pB F$ H1?:   G$ T9gֳgֳ?   J20b   pB H$ H1?  I$ Tܸ9gֳgֳ? WJ J32b    J$  BCZDEF1?YY @e J  pB K$ H1? +  L$ T9gֳgֳ?f   J14b   jB M$ B1?e ^^f pB N$ H1?   O$ T9gֳgֳ?~ \+  I2b   pB P$ H1?| q  Q$ TH9gֳgֳ?C   J16b    R$ T9gֳgֳ?V  Q Cache hit b    S$ T9gֳgֳ?n .  OCacheb   T$ TH9gֳgֳ? MTLBb   U$ T9gֳgֳ?I ;  W Byte offset P b    V$ T0Hgֳgֳ? m  MIndexb    W$ T0Hgֳgֳ?P n w  KTagb   jB X$ B1?FF Y$ TdHgֳgֳ?l QTLB hitb    Z$ T!Hgֳgֳ?p  gDECStation 3100b   H $ 0޽h ? 333gggy___PPT10Y+D=' = @B + 7L0  pJ|(  |d | <1?  |  `0xaxa1 ?P`   dR | <1?XB | 0D1? `  | <\91? $  5Increasing distance from the processor in access time26* | <A1?P ` p 7L1$XB | 0D1? @ XB  | 0D1?i 0i   | <,D1?9 P `  7L2$  | <xG1? @@  A Main Memory    | <K1?Y P@ GSecondary Memory^B  | 6D1?y | HHO1?I 0 = Processor dB | <D1?99 | <S1?i@P _+(Relative) size of the memory at each level,,^F @``  | @yfB | 6D1?@@`  | <PX1?@`  &Inclusive what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM&s jF  ) I  |    ) lB | <D1? ) lB | <DjJ? i )lB | <DԔ?  I lB | <DjJ? I F  8-  |    | HT^1? 8"  ^4-8 bytes (word)2  | <d1? yM  ? 1 to 4 blocks | Hg1? Y -  o!1,024+ bytes (disk sector = page)2" | <l1? m `8-32 bytes (block)2  | Z 8c 8c1 ?  Take advantage of the principle of locality to present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technology. qK/8c8X2 | <o? @,$D0H | 0޽h ? U>=UU(ia___PPT10A+Y D%' = @B D' = @BA?%,( < +O%,( < +D' =%(D' =%(Dg' =4@BB7BB%(D' =1:Bvisible*o3>+B#style.visibility<*|%(D' =+4 8?fCB#ppt_w*0.70BCB#ppt_wB*Y3>B ppt_w<*|D' =+4 8?\CB#ppt_hBCB#ppt_hB*Y3>B ppt_h<*|D' =-g6B fade*<3<*|+ L0  OP(  r  S P`     S $P`<$0  H  0޽h ? X(=^___PPT10b.&@'++D' = @B D' = @BA?%,( < +O%,( < +D,' =%(%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*2%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*2v%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*v%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*M%(D' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*M%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*<%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*<%(+8+0+I + L0 0O%43(  r  S IP`  I d  <1? (x XB  0D1?(x XB  0D1?@(x @XB  0D1?(x XB  0D1?` (x ` XB   0D1? (x d  <1?l XB  0D1?0 l0 XB  0D1? l XB  0D1?P lP XB  0D1? l XB  0D1?p lp XB  0D1? l XB  0D1? l jb  BG&1? l   HI1?T 4 SProgram 1 virtual address space    HD$I1? = main memory dB  <D1?P, l dB @ <D1?,, dB @ <D1?@, dB   <D1? , dB ! <D1? , l dB " <D1? , `0 dB #@ <D1?P , dB $ <D1?` , l dB & <D1?@ , ldB ( <D1? , l@dB ) <D1?@ \, ` * Zp I 8c 8c1 ? 0 6A program s address space is divided into pages (all one fixed size) or segments (variable sizes) The starting location of each page (either in main memory or in secondary memory) is contained in the program s page tableHb{*3p  @d , <1? (x XB - 0D1?P (x P XB . 0D1? (x XB / 0D1?p(x pXB 0 0D1?(x  3 H$HI1?@ T  WProgram 2 virtual address space  H  0޽h ? X(=^___PPT10i.,$+D=' = @B +] E Lb(  ~  s *|IP  I   HPI1? DVirtual Address (VA)d  <1?WGdB  <D1?WG  HPI1?n&rU = Page offset   HdVI1?nZ U EVirtual page number  HZI1?a o31 30 . . . 12 11 . . . 0ppl  0  G 0 ,$D0l  <1?  lB   <D1?     Hp_I1?& r  = Page offset    HdI1?   FPhysical page number   H4hI1?E ` 0  EPhysical Address (PA)  HiI1?   c29 . . . 12 11 0dd'l @  G@G ,$D 0   TAo?5%p    HpI1?v  = Translation rB  BD1?0 0 rB  BD1?0  0 fB  6D1?@@    fzI 8c 8c1 ? P`<$0 I & @M  ZI 8c 8c1 ?P` _A virtual address is translated to a physical address by a combination of hardware and softwareH`*H  0޽h ? X(=^3 + ___PPT10 +D ' = @B Dr ' = @BA?%,( < +O%,( < +D' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =-o6Bwipe(up)*<3<*D' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*j%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*j%(+8+0+I ++ L0 >6O@X(  x  c $IP`  I d  <1?, XB  0D1?:, :XB  0D1?, XB  0D1?Z , Z XB  0D1? , XB  0D1?z , z XB   0D1? , XB   0D1? , XB   0D1?* , * XB   0D1? , XB   0D1?J , J d  <1?\ XB  0D1?\XB  0D1?1\1XB  0D1?\XB  0D1?Q \Q XB  0D1? \ XB  0D1?q \q XB  0D1? \ jb  BG 1?Q ,  HxI1?`q  mPhysical page base addr  H8I1?j  Q  ? Main memory dB  <D1?` dB  <D1? `dB  <D1?`dB  <D1?1 q dB  <D1? ` dB  <D1?` dB  <D1?` ` dB   <D1? ` dB ! <D1? 1dB " <D1?@` dB # <D1?q !d $ <1?A L d % <1?Ld & <1?LQXB ' 0D1?ll  ( HI1?`h @ Disk storage d ) <1?0 * HLI1?   @Virtual page # + HЩI1? 3V , HI1?  G1 1 1 1 1 1 0 1 0 1 0 @ HI1?  ]Page Table (in main memory)& Jl 0  R0 ,$D 0fB - 6D1?  `B F 0D1?0 d G <1?0 H HI1?,  8OffsetB I 6D1? ,$D 0d K <1?0  L HI1?Y @ APhysical page #d M <1?0 `  N HT1I1?p t W 8Offsetl `0  S0` ,$D 0`B O 0D1?`0` `B P 0D1?`) )fB Q 6D1? ) l 0 @  X0 @ ,$D 0`B T 0D1?0 0 `B U 0D1?0 ` `B V 0D1?` ` @ fB W 6D1?` @ @ H  0޽h ? X(=^  ___PPT10 .,$+֫SD ' = @B Dq ' = @BA?%,( < +O%,( < +D' =%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*R%(D' =-o6Bwipe(up)*<3<*RD' =%(D' =%(D7' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*I%(D' =-s6Bwipe(down)*<3<*ID' =%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*S%(D' =-o6Bwipe(up)*<3<*SD' =%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*X%(D' =-o6Bwipe(up)*<3<*X+ L0 O#(  r  S xIP`  I r  S I@P`, I F X  (P`B  08c?x`B  08c? h`B B 08c?X  Z@I 8c 8c1? 9CPUU    `Ixaxa8c?0( h e Trans- lation    `Ixaxa8c? 0 h ;Cache    `Ixaxa8c?8p A Main Memory  fB   68c?xfB   68c?(  fB  68c? xx`B B 08c?P`B  08c?XX`B B 08c?``B  08c?0fB B 68c?88`B  08c?PPfB B 68c? X `B B 08c?`  fB  68c?h h f2  68c?Pp`  ZA 8c 8c1? 8VAU  ZA 8c 8c1?8 P  8PAU  ZA 8c 8c1? h :missU  Z$ A 8c 8c1?h @h  9hitU  ZA 8c 8c1? :dataUD  Z<A 8c 8c1 ? 0Y,$0 This makes memory (cache) accesses very expensive (if every access was really two accesses) The hardware fix is to use a Translation Lookaside Buffer (TLB)  a small cache that keeps track of recently used address mappings to avoid having to do a page table lookup8 # {H  0޽h ? X(=^___PPT10.90ov+cDDO' = @B D ' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+A +, L0 ""@OHY0 r"(  x  c $4"AP`  A d  <1?, XB  0D1?:, :XB  0D1?, XB  0D1?Z , Z XB  0D1? , XB   0D1?z , z XB   0D1? , XB   0D1? , XB   0D1?* , * XB   0D1? , XB  0D1?J , J d  <1?\ XB  0D1?\XB  0D1?1\1XB  0D1?\XB  0D1?Q \Q XB  0D1? \ XB  0D1?q \q XB  0D1? \ jb  BG 1?Q ,  H8!1?`q  mPhysical page base addr  H1A1?j  Q  ? Main memory dB  <D1?` dB  <D1?A\dB  <D1?`dB  <D1?1 q dB   <D1? ` dB ! <D1?` dB " <D1?` ` dB # <D1? ` dB % <D1? 1dB & <D1?@` dB ' <D1?q !d ) <1?A L d * <1?Ld + <1?LQXB - 0D1?ll  . HAA1?`h @ Disk storage d / <1?0 0 HEA1?L @Virtual page # 1 HJA1? 3V 2 HHA1?  G1 1 1 1 1 1 0 1 0 1 0^B 4 6D1?  S l  / Y /,$D0r 7 B1? fB 9 6D1? fB : 6D1? ))fB ; 6D1? fB < 6D1? IIr ? B1?   fB @ 6D1?  fB A 6D1? ) )fB B 6D1?  fB C 6D1? I I F N(PA1?   ; 1 1 1 0 1 fB G 6D1?  H NXA1?\ X , 5Tag I N^A1? /0 mPhysical page base addr J NXdA1? X, 3V K NlbA1?   7TLB M HhjA1?(  aPage Table (in physical memory)&  \l  !`  U` ` ,$D 0rB N BD1? !`@rB O BD1? \ArB P BD1? A`` rB Q BD1? 1` XB R 0D1?0 Pl 0 0 Xx x,$D 0fB E 6D1?0 0fB V 6D1? 0 0H  0޽h ? X(=^p h ___PPT10H .,$+ZD ' = @B D' = @BA?%,( < +O%,( < +D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*Y%(D' =%(D' =%(D7' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*X%(D' =-s6Bwipe(down)*<3<*XD' =%(D' =%(D3' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*U%(D' =-o6Bwipe(up)*<3<*U+  L0 80O (  r  S D}AP`  A r  S ~A@P`, A d  <1?0xX  TA 8c 8c1?Dxp {E V Virtual Page # Physical Page # Dirty Ref AccessFUFXB  01?000XB @ 01?@P P XB  01?@XB   01?@XB   01?x`XB   01?@   Z+B#style.visibility<* %(+8+0+ A +% L0 91N&- (  r  S (AP`  A   c $A0 PG<$0 A [8 p  - fB  68c?8X8fB  68c?`@`fB B 68c?h   `A 8c 8c1?  9CPUU    fAxaxa8c?P  @ TLB Lookup      fԛAxaxa8c? P  ;Cache    fdAxaxa8c?XX A Main Memory  lB   <8c?hlB   <8c? p lB  <8c?(HfB B 68c?0X0fB  68c?8 fB  68c?  fB  68c? @  lB  <8c?`p plB B <8c? @@lB  <8c? @    `A 8c 8c1?x 8VAU   `A 8c 8c1?   8PAU   `A 8c 8c1?H :missU   `A 8c 8c1?@ @ k 9hitU   `ĮA 8c 8c1?0   :dataU   f$Axaxa8c?  e Trans- lation   ` A 8c 8c1? p # 9hitUlB   <8c?HH !  `زA 8c 8c1?@k :missUfB " 68c?P P@ fB # 68c?XH H lB $ <8c?  P lB %B <8c?   '  `|A 8c 8c1? p # K t,U (  `PvA 8c 8c1?x+ L t,U`B + 0Do?@ `B , 0Do? @p @H  0޽h ? X(=^___PPT10 .O+XFD| ' = @B D7 ' = @BA?%,( < +O%,( < +Da' =%(%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*7%(D' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*7%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<**%(D' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<**i%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*i%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+A +' L0 & P +(  x  c $AP`  A    + #"*  A  BA1?   Q 0.01% to 2%  8c`  Bܼ?1?P    Y0.00001% to 0.0001%8c`  B?1? P  P Miss rates  8c`  Bܾ?1?Z   P 10 to 1000  8c`  B@?1?P Z   _10,000,000 to 100,000,0008c`   B?1?Z P   [Miss penalty (clocks)8c`   B?1?^Z  M4 to 328c`   BX ?1?P ^Z  T4000 to 64,0008c`   B?1?^P Z  TBlock size (B)8c`   B8?1?^ P 0.25 to 16  8c`  BA1?P ^ ^250,000 to 1,000,000,0008c`  B.?1?P ^ UTotal size (KB)8c`  B/?1? W16 to 512 entries8c`  B<8?1?P  ]16,000 to 250,000 words8c`  B8c``B  0o ?ZB  s *1 ?ZB  s *1 ?ZB  s *1 ?^^ZB  s *1 ?Z Z ZB  s *1 ?  `B  0o ?  `B  0o ? ZB  s *1 ?P P ZB  s *1 ? `B   0o ? H  0޽h ? X(=^___PPT10i.0t{n+D=' = @B +  IL0   0PXh (  x  c $tP`    h i X #"i4  B|m?1?P i 2 TLBs for instructions and 2 TLBs for data Both L1 TLBs fully associative with ~LRU replacement Both L2 TLBs are 4-way set associative with round-robin LRU Both L1 TLBs have 40 entries Both L2 TLBs have 512 entries TBL misses handled in hardwaret1818c`  B?1?P  y AMD Opteron  8c` ' B0?1?P i O1 TLB for instructions and 1TLB for data Both 4-way set associative Both use ~LRU replacement Both have 128 entries TLB misses handled in hardware8c` ( B|?1?i XTLB organization8c` ) B?1?P  TIntel P4  8c` * B ?1? @8c``B + 0o ?ZB , s *o ?`B 7 0o ?ii`B 8 0o ?iZB 9 s *o ?i`B : 0o ?iZB ; s *1 ?P P iH  0޽h ? X(=^___PPT10i.߽p-+D=' = @B +! L0   PP1jM (  r  S P`    P@` j #"2&@P`  ( BP{?1? ` >8c` ' Bx?1?0  R Hit   8c` & B$?1? 0 LMiss8c` % BV1?P  LMiss8c`   BV1? `  >8c`  B$V1?0   R Miss/ Hit  8c`  B!V1? 0  LMiss8c`  B4*V1?P   KHit8c`  B2V1? `  >8c`  B:V1?0   LMiss8c`  BCV1? 0  LMiss8c`  BKV1?P   LMiss8c`  BSV1?`  >8c`  B4\V1?0  MMiss 8c`  B|dV1?0  KHit8c`  B|fV1?P  LMiss8c`  BuV1?` >8c`  BwV1?0 KHit8c`  BV1?0 KHit8c`  BV1?P LMiss8c`  B8c`  BV1?0 MMiss 8c`  BV1?0 KHit8c`   BV1?P KHit8c`   B,V1?` >8c`   BV1?0 KHit8c`   BLV1?0 KHit8c`   BV1?P KHit8c`  BV1?@` j$Possible? Under what circumstances?%%8c`  BxV1?0@ MCache8c`  BPV1?@0 R Page Table  8c`  BpJ1?P@ KTLB8c``B ) 0o ?P@`@ZB * s *o ?P`ZB + s *1 ?P`ZB , s *1 ?P`ZB - s *1 ?P`ZB . s *1 ?P ` ZB / s *1 ?P ` ZB 0 s *1 ?P ` `B 2 0o ?P``B 3 0o ?P@PZB 4 s *1 ?@ZB 5 s *1 ?0@0ZB 6 s *o ?@`B 7 0o ?`@`H  0޽h ? X(=^___PPT10i.p+D=' = @B +< L0 ))P88%)(  x  c $\JP`  J  P@` # #"2& @P` J  B01? ` >8c`  B1?0  R Hit   8c`  B81? 0 LMiss8c`  Bn1?P  LMiss8c`  Bs1? `  >8c`   B4~1?0   R Miss/ Hit  8c`   Bp1? 0  LMiss8c`   B1?P   KHit8c`   B$1? `  >8c`   B.1?0   LMiss8c`  B$61? 0  LMiss8c`  B>1?P   LMiss8c`  BE1?`  >8c`  BO1?0  MMiss 8c`  BV1?0  KHit8c`  BpQ1?P  LMiss8c`  Bxc1?` >8c`  Be1?0 KHit8c`  B{1?0 KHit8c`  B܃1?P LMiss8c`  B1?` >8c`  B|1?0 MMiss 8c`  B|1?0 KHit8c`  B41?P KHit8c`  B\1?` >8c`  BЮ1?0 KHit8c`  B\1?0 KHit8c`  B$Ʋ1?P KHit8c`   BDz1?@` j$Possible? Under what circumstances?%%8c` ! BTײ1?0@ MCache8c` " Bز1?@0 R Page Table  8c` # Bڲ1?P@ KTLB8c``B $ 0o ?P@`@ZB % s *o ?P`ZB & s *1 ?P`ZB ' s *1 ?P`ZB ( s *1 ?P`ZB ) s *1 ?P ` ZB * s *1 ?P ` ZB + s *1 ?P ` `B , 0o ?P``B - 0o ?P@PZB . s *1 ?@ZB / s *1 ?0@0ZB 0 s *o ?@`B 1 0o ?`@` 2 H1?,$0 X&Yes  what we want!X 3 H1?6,$0 zYes  although the page table is not checked if the TLB hits>> 4 H,1?b,$0 r@Yes  TLB miss, PA in page table!!L 5 H1? ,$0 nYes  TLB miss, PA in page table, but data not in cache88 6 H1?  ,$0 R Yes  page faultr 7 H/1?  ,$0 Impossible  TLB translation not possible if page is not present in memoryKK^ 8 H11? wz,$0 Impossible  data not allowed in cache if page is not in memoryAAH  0޽h ? X(=^___PPT10.p+1iD' = @B D' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*2%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*3%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*4%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*5%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*6%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*7%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*8%(++0+2 ++0+3 ++0+4 ++0+5 ++0+6 ++0+7 ++0+8 +f- GL0 e,],OOQ+(  r  S $/P`   r  S d?P`    Ho?  0  Ho?J   0j  B1? J  |B  TD1?``   N]1?T ;  7Tag   Nc1?TY;  8Dataj   B1?^ J  |B   TD1?^ `` B   ZD1? ^ B   ZD1? 22^ j2  B1? J `   Nj1?M t <4  5=B  ZD1? j  B1?  |B  TD1?   Nz1?T;  7Tag  No1?T;  8Dataj  B1?^  |B  TD1?^  B  ZD1? ``^ B  ZD1? ^ j2  B1?    N u1?M 4  5=B  ZD1? `` v  N1?^  |B  TD1? V  |B  TD1? V V  B  ZD1? B   ZD1?  v ! N1?^ a B " ZD1? e p" # H1? Uu|B $ TD1? |B % TD1? `` |B & TD1? w |B ' TD1? ` |B ( TD1? ww|B ) TD1? B * ZD1?u2 + N`}1? = Cache Hit  jr , B1?B - ZD1? |B . TD1?H 2TH B / ZD1?H TT|B 0 TD1? 22H B 1 ZD1?2 2 Nt1? @ Desired word  B 3 ZD1?**|B 4 TD1? > > B 5 ZD1?> 1j 6 B1?0|B 7 TDo?p`|B 8 TD1?P |B 9 TD1?0P|B : TD1?P P|B ; TD1?0xx|B < TD1?x B = ZD1?  p |B > TD1?HH0j ? Bo?PP |B @ TD1?PHHP |B A TD1?0|B B@ TD1?B C ZD1?P|B D TD1?P  |B E TD1? h B F ZD1? h h p  G N 1?@H'  >VA Tag H N1?\~  >PA TagB J ZD1?P ((@  K N41?@ T'  ?TLB HitB L ZD1?   N H1?p W K2-way Associative Cache O H1?0  : Index P H`1? 0  :PA Tag Q Hढ़1?@  > Block offset H  0޽h ? X(=^___PPT10i.+D=' = @B +* FL0 Oo(  r  S lP`   r  S @P`   F X v  Pp   Z䮝 8c 8c1?~ v :dataU`B  01?`B  01?P`B B 01?``   Z 8c 8c1?&: 9CPUU    `0xaxa1?+ P e Trans- lation    `xaxa1?+ 8 ;Cache    `xaxa1?U b A Main Memory  fB   61?#fB  61?&#fB  61? M`B B 01? HMH`B  01? L `B B 01?d `B  01?\\l`B  01?  fB B 61?  `B B 01?+fB  61?f2  61?    Z0ɝ 8c 8c1?d 8VAU  ZΝ 8c 8c1?d 9hitU`B  01?  Z̝ 8c 8c1?^ Xv  8PAUj  Z@ 8c 8c1 ? P`,$0 F but Two different virtual addresses can map to the same physical address (when processes are sharing data), i.e., two different cache entries hold data for the same physical address  synonyms Must update all cache entries with the same physical address or the memory becomes inconsistentJ` `H  0޽h ? X(=^___PPT10.:ܔ+DO' = @B D ' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+ + L0 pO*(  r  S 8P`   x  c $ @P0F  H  0޽h ? X(=^___PPT10i.1+D=' = @B + HL0 O:(  r  S P`     S $I@P`  " (;PpH  0޽h ? X(=^___PPT10i.?%2+D=' = @B +hJ0 ( J(    S ~>dd1 ? J  >     T1 ?2   >H  0\j ? a(Q0 e]PO(  ^  S s4   >W  c $t!> K  > The page size is 212 = 4KB, the number of physical pages allowed in memory is 218, the physical address space is 1GB and the virtual address space is 4GB6;IH  0\j ? X(=^80___PPT10./8v0 OH(  ^  S s4   >  c $D)> K  > >*Doing synonym updates requires significant hardware  essentially an associative lookup on the physical address tags to see if you have multiple hitsH  0\j ? X(=^80___PPT10.:Ln0 O\(  ^  S s4   >  c $/> K  > ROverlapped access only works as long as the address bits used to index into the cache do not change as the result of VA translation This usually limits things to small caches, large page sizes, or high n-way set associative caches if you want a large cache4W H  0\j ? X(=^80___PPT10.=mfNw0 nfO (  ^  S s4   >`   c $d:> K  >  Let s summarize today s lecture. I know you have heard this many times and many ways but it is still worth repeating. Memory hierarchy works because of the Principle of Locality which says a program will access a relatively small portion of the address space at any instant of time. There are two types of locality: temporal locality, or locality in time and spatial locality, or locality in space. So far, we have covered three major categories of cache misses. Compulsory misses are cache misses due to cold start. You cannot avoid them but if you are going to run billions of instructions anyway, compulsory misses usually don t bother you. Conflict misses are misses caused by multiple memory location being mapped to the same cache location. The nightmare scenario is the ping pong effect when a block is read into the cache but before we have a chance to use it, it was immediately forced out by another conflict miss. You can reduce Conflict misses by either increase the cache size or increase the associativity, or both. Finally, Capacity misses occurs when the cache is not big enough to contains all the cache blocks required by the program. You can reduce this miss rate by making the cache larger. There are two write policy as far as cache write is concerned. Write through requires a write buffer and a nightmare scenario is when the store occurs so frequent that you saturates your write buffer. The second write polity is write back. In this case, you only write to the cache and only when the cache block is being replaced do you write the cache block back to memory. +3 = 77 min. (Y:57)MM $ HH  0\j ? X(=^80___PPT10.?0kZcz0 @Ps(  d  c $s4   >  s *A> K  > ]IA trace cache finds a dynamic sequence of instructions including taken branches to load into a cache block. Thus, the cache blocks contain dynamic traces of the executed instructions as determined by the CPU rather than static sequences of instructions as determined by memory layout. It folds branch prediction into the cache.H  0\j ? X(=^80___PPT10.d0 bZP$(  $ $  T1 ?1   5 $ C xP5gֳgֳ ? I  5 ^` H""DDffH $ 0\j ? a(0 bZP,(  , ,  T1 ?1   4 , C x>4gֳgֳ ? I  4 ^` H""DDffH , 0\j ? a(0 bZQ4(  4 4  T1 ?1   3 4 C x3gֳgֳ ? I  3 ^` H""DDffH 4 0\j ? a(0 bZ0Q<(  < <  T1 ?1   3 < C x3gֳgֳ ? I  3 ^` H""DDffH < 0\j ? a(0 bZPQD(  D D  T1 ?1   3 D C x3gֳgֳ ? I  3 ^` H""DDffH D 0\j ? a(0 bZpQL(  L L  T1 ?1   ' L C x.'gֳgֳ ? I  ' ^` H""DDffH L 0\j ? a(0 QTM(  T T  T1 ?1   'y T C x4c'gֳgֳ ? I  ' QThe virtual page number is used to index the page table. If the valid bit is on, the page table supplies the physical page number (i.e.,., the starting address of the page in memory) corresponding to the virtual page. If the valid bit is off, the page currently resides only on disk, at a specified address. In many systems, the table of physical page addresses and disk page addresses, while logically one table, are stored in two separate data structures. Dual tables are justified in part because we must keep the disk addressers of all the pages, even if they are currently in main memory.RRbR H""DDffH T 0\j ? a(0 bZQ`(  ` `  T1 ?1   ' ` C x'gֳgֳ ? I  ' ^` H""DDffH ` 0\j ? a(0 bZQh(  h h  T1 ?1   # h C x #gֳgֳ ? I  # ^` H""DDffH h 0\j ? a(0 bZRp(  p p  T1 ?1   C p C x@Cgֳgֳ ? I  C ^` H""DDffH p 0\j ? a(0 bZ Rx(  x x  T1 ?1    x C xgֳgֳ ? I   ^` H""DDffH x 0\j ? a(0 bZ@R(     T1 ?1     C xgֳgֳ ? I   ^` H""DDffH  0\j ? a( 0 `RY(     T1 ?1     C xmgֳgֳ ? :?   ]# of virtual pages does not need to be equal to # of pages addressable with physical address.^^b^ H""DDffH  0\j ? a(0 bZR(     T1 ?1     C xvgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZR(     T1 ?1     C xgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZR(     T1 ?1     C xgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZS(     T1 ?1     C x<[gֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZ S(     T1 ?1     C x,gֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZ@S(     T1 ?1     C xgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZpS(     T1 ?1     C x ygֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZS(     T1 ?1     C xgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZS(     T1 ?1     C xHgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZS(     T1 ?1     C x֫gֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZS(     T1 ?1     C xLgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 Ta(     T1 ?1   4  C xT4gֳgֳ ?~ RS  4 GThe TLB contains a subset of the virtual-to-physical page mappings that are in the page table. (The TLB mappings are shown in color.) Because the TLB is a cache, it must have a tag field. If there is no matching entry in the TLB for a page, the page table must be examined. The page table either supplies a physical page number for the page (which can then be used to build a TLB entry) or indicates that the page resides on disk, in which case a page fault occurs. Since the page table has an entry for every virtual page (it is not a cache, in other words), no tag field is needed.6Hbb3bH H""DDffH  0\j ? a(0 bZ0T(     T1 ?1   /  C x/gֳgֳ ? I  / ^` H""DDffH  0\j ? a(60 `T(     T1 ?1     C x4gֳgֳ ? I   If the TLB generates a hit, the cache can be accessed with the resulting physical address. If the operation is a write, the cache entry is overwritten and the data is sent to the write buffer; remember, though, that a cache write miss cannot occur for the DECStation 3100 cache, which uses one-word blocks and a write-through from memory. In actuality, the TLB does not contain a true dirty bit; instead, it uses the write protection bit to detect the first write. How this works will be explained in the next section. Notice that a TLB hit and a cache hit are independent events; this is examined further in the exercises at the end of this chapter.b H""DDffH  0\j ? a(0 bZT(     T1 ?1     C x4ɧgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZT(     T1 ?1     C xxԧgֳgֳ ? I   ^` H""DDffH  0\j ? a(0 bZT (       T1 ?1   9   C x#9gֳgֳ ? I  9 ^` H""DDffH   0\j ? a(0 bZT((  ( (  T1 ?1   H ( C xD9gֳgֳ ? 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Computer Architecture Lecture 19 Janie IrwinDavid L. Mills598Microsoft PowerPoint 4.0@%.,@e,5ò@ (@ / G8;    --$  --'@"Arial-. 2 " CSE431 L22 y. "SystemD-@"Arial-.  2 bTLBs.-@"Arial-.  2 z..-@"Arial-.  2 }1.-@"Arial-. 2 LIrwin, PSU, 2005 .-=-=-8(223(3(2(556(6(5--'@"Arial-. =2 Virtual Memory   .-՜.+,0    YLetter Paper (8.5x11 in),5% =Times New RomanArial WingdingsMonotype Sorts 新細明體Tahoma mjicse431 WorksheetVirtual MemorySlide 2Slide 3Structure of Virtual MemorySlide 5Slide 6Slide 7 TechnologySlide 9Virtual Address Mapping TerminologyVM Simplifies Loading"Address Translation Consideration Slide 14 Slide 15 Slide 16What happens on a write ? Page Size Selection ConstraintsPage Size Selection An Example Slide 21 Slide 22 Techniques for Reducing PT Size Slide 24 Slide 25VM: Implementation IssuesFast Address TranslationPage Fault Handling Slide 29 Slide 30 TLB Design Slide 32 Slide 33Translation Lookaside Buffer Slide 35 Slide 36Review: The Memory HierarchyVirtual Memory%Two Programs Sharing Physical MemoryAddress TranslationAddress Translation Mechanisms Virtual Addressing with a Cache Making Address Translation Fast%Translation Lookaside Buffers (TLBs)A TLB in the Memory Hierarchy&Some Virtual Memory Design Parameters!Two Machines’ Cache ParametersTLB Event CombinationsTLB Event CombinationsReducing Translation Time%Why Not a Virtually Addressed Cache?The Hardware/Software BoundarySummary  Fonts UsedDesign TemplateEmbedded OLE Servers Slide Titles5&_0David L. MillsDavid L. Mills  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Root EntrydO)Pictures$Current UserSummaryInformation(PowerPoint Document(DocumentSummaryInformation8