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' ! ,YkG= ;$&?mt<=?@CDEFG JKLMNOPQRST&UVWX&YZ[\&]^_` abcdefghijklmnopor$3x!tV$dir$fL4³@1ii"$.W DCb!k'V"$z*<ڊ7ΫCD ("${}f5@2$ʓB(Data-path control unit design Pipeline stalls on cache misses??b  ? 8!Actions Needed on an I-Cache Miss"P"` " 1. Compute the value of PC-4. 2. Instruct the main memory to perform a read and wait for the memory to complete its access. 3. Write the cache entry, putting the data from memory in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on. 4. Restart the instruction execution at the first step, which will re-fetch the instruction, this time finding it in the cache.(`b  9A Case Study: DEC Station 3100P`  Separate I-Cache and D-Cache  Write-through policy One-word-line simplifies write-miss handlingaab a :How to Handle Read/Write`  Write Write-through: for both write hit/miss 1. Index the cache using bits 15-2 of the address. 2. Write both the tag portion (using bits 31 - 16 of the address) and the data portion with the word. 3. Also write the word to main memory using the entire address. D bb`  ;<Performance Penalty due to Write-Through on DEC Station 3100(=P,`b = CPI without cache misses: 1.2 (gcc), but with each write takes 10 cycles: CPI becomes 2.3 (gcc) Note: in gcc, 11% of instructions are stores, each takes 10 cycles Solution: write buffers (in DEC Station 3100: size=4)R`D6abbubZ  9     m <  =Combined I-Cache/D-Cache?2 b`b  ]Hit ratio: Combined may be better: In DECStation 3100: 4.8% vs 5.4% Bandwidth considerations4#"^b@'       >  The primary method of achieving higher memory bandwidth is to increase the physical or logical width of the memory system. In this figure there are two ways in which the memory bandwidth is improved. The simplest design, (a), uses a memory where all components are one word wide; (b) shows a wider memory, bus, and cache while (c) shows a narrow bus and cache with an interleaved memory.8byb b  'Review: Major Components of a Computer ]% Processor-Memory Performance Gap 6"The  Memory Wall )Logic vs DRAM speed gap continues to grow**"`&(Memory Performance Impact on PerformanceSuppose a processor executes at ideal CPI = 1.1 50% arith/logic, 30% ld/st, 20% control and that 10% of data memory operations miss with a 50 cycle miss penaltyP!9{9{,6a'The Memory Hierarchy GoalFact: Large memories are slow and fast memories are small How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)? 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TDatapath d   <8c?`` \    Z5xaxa1?O$  KSecondary Memory (Disk)   <8c? f ,$D0   Zxaxa1?G,$0 DOn-Chip Components^B  6o?P ^B  6o? M d  <8c?J aA   ZZxaxa1? R  SRegFilex  PA8c?10% P0 x  PA8c?10%p   Z xaxa1?` f  JMain Memory (DRAM)   `Zp xaxa1?r U  B Data Cache  x  PA8c?10% P    `Zxaxa1?d  ] Instr Cache  x  PA8c?10% 0  @ T1?   <ITLB @ T1? @  <DTLB  B6'Ԕ?p` ,$D0 @ B81?4,$0 UeDRAM6'  Z" 8c 8c1?   "Speed (%cycles):  s 1 s 10 s 100 s 1,000 s8hU#V  Z( 8c 8c1? E jSize (bytes): 100 s K s 10K s M s G s to T sLqU  5'G1  TP0 8c 8c1?0 k Cost: highest lowest&lU]   Z4 8c 8c1 ? H 1By taking advantage of the principle of locality Can present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technologyH1 qK lK18c8XH  0޽h ?   ___PPT10 .+4D ' = @B D ' = @BA?%,( < +O%,( < +D ' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(|D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%('D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+p+0+  ++0+ +Y! L0  ? (  d  <1?    `$Mxaxa1 ?P`   dR  <1? XB  0D1? ` #  <LO1? D ,$0 5Increasing distance from the processor in access time26*  <U1?P `  7L1$XB   0D1?@ XB   0D1? 0    <Y1?YP ` @ 7L2$   <]1?9 @@  A Main Memory     <a1?y P`  GSecondary MemoryB  6D1? ,$D0  H1?   = Processor B  <D1?Y Y ,$@0  <1? @p,$0 _+(Relative) size of the memory at each level,,z @``   @ ,$D0fB  6D1?@@`   <p1?@`  &Inclusive what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM&s j8  ) I  )  I lB  <D1? ) lB  <DjJ? i )lB  <DԔ?  I lB  <DjJ? I l  8-  8 - ,$D0  N 1? 8"  ^4-8 bytes (word)2   Bt 1? yM  ? 1 to 4 blocks  N1? Y -  o!1,024+ bytes (disk sector = page)2"  B1? m `8-32 bytes (block)2 H  0޽h ? U>=UU(  ___PPT10 +elD( ' = @B D ' = @BA?%,( < +O%,( < +D' =%(Du' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(Du' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(+p+0+ ++0+ + L0 z@(    C x4' 8c 8c1 ?R+     C xN 8c 8c1 ? 0 *   t  ZX( 8c 8c1 ?` ,$0 Main Memory uses DRAM for size (density) High density (1 transistor cells), low power, cheap, slow Dynamic: needs to be  refreshed regularly (~ every 8 ms) 1% to 2% of the active cycles of the DRAM Addresses divided into 2 halves (row and column) RAS or Row Access Strobe triggering row decoder CAS or Column Access Strobe triggering column selector)u*1gu*1              d  <1?^B  6Do?ppXB @ 0D1? ^B  6Do?XB  @ 0D1?``^B   6Do?  XB  @ 0D1?`P   <l81?P < Dout[15-0]    <<1?l @ SRAM 2M x 16    <TA1?` w ; Din[15-0]   <D1?0  9Address  <G1? 0  = Chip select   <pK1?p  ? Output enable  <1? t > Write enable ^B  6D1?00^B  6D1?pp^B  6D1?  <l1?P 416  <T 1?PP 416  <x 1?P 421H  0޽h ? X(=^___PPT10+PQFDO' = @B D ' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+ + L0 `D$(  r  S P`   r  S @P`  H  0޽h ? X(=^___PPT10i.8v+D=' = @B +" L0 ?++I(    S ~! 8c 8c1 ?_   ~  VA1?20% |   Z# 8c 8c1?pH  JR o w D e c o d e rUd  <8c?X XB  08c?`h( `XB  08c?Ph( PXB  0p?@p @XB   08c?0h( 0XB   08c? h( XB   08c?h( XB   08c? h( XB   08c? h( dB  <Ԕ?    ZD. 8c 8c1? (  A row address U d  <8c? ( jB  BԔ? @@X  Z3 8c 8c1?p # Fdata bit or wordUXB  08c?@@ XB  08c?00 XB  08c?   XB  08c? XB  08c?  XB  08c?  XB  08c?     `$9 8c 8c 1? FRAM Cell ArrayUz  x     x ,$D0fB  61? l    Z> 8c 8c1?( x Eword (row) lineUz     ,$D0fB  61? <    ZC 8c 8c1? s Fbit (data) linesUz   !  ,$D0fB " 61?  D # T@Gxaxa1? r@Each intersection represents a 6-T SRAM cell or a 1-T DRAM cellAAXB $ 0o?  %  `L 8c 8c1? (  V Column Selector & I/O Circuits!! &  `O 8c 8c1?@ X  Bcolumn addressjB '@ BԔ? 0  ( TPxaxa1? ` 0 ,$D0 mOne memory row holds a block of data, so the column address selects the requested bit or word from that blockNnRXB ) 0o? 0 XB * 0p? 0 XB + 0jJ? 0 H  0޽h ? X(=^ w ___PPT10W +5D ' = @B D ' = @BA?%,( < +O%,( < +D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*!%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*(%(+8+0+( +), L0 8+0+?XX*(  F %Q B   0\\   VA1?20%IQ `B  08c?- `B  08c?-r r`B  0p?5b b`B  08c?-R R`B  08c?-B B`B   08c?-2 2 `B   08c?-" " `B   08c?-  `B   08c?: `B   08c?: `B  08c?: `B  08c?: `B  08c?: `B  08c?  : `B  08c?  : `B  0p?  B `B  0Do?%B    Zx  8c 8c1?  `  <data bit   Z 8c 8c1?0 S >data bit U   C xh 8c 8c1 ?l`     Z 8c 8c1?   JR o w D e c o d e rUd  <8c?* dB  <Ԕ? ee   Z 8c 8c1? e  A row address U   Z@ 8c 8c1?b   X Column Selector & I/O Circuits!U!d  <8c?:    Zd 8c 8c1? ]X  Dcolumn addressUdB @ <1? 0   Z  8c 8c1?0@  >data bit U  " Z( 8c 8c1?p#  Eword (row) lineU^B # 61?  $ Z, 8c 8c1? @c Fbit (data) linesU % T0xaxa1?! _-Each intersection represents a 1-T DRAM cell.. &  d2 8c 8c1 ?    pr ' H1? @  9. . .F %Q B  1 `P|  2 VA1?20%IQ `B 3 08c?- `B 4 08c?-r r`B 5 0p?5b b`B 6 08c?-R R`B 7 08c?-B B`B 8 08c?-2 2 `B 9 08c?-" " `B : 08c?-  `B ; 08c?: `B < 08c?: `B = 08c?: `B > 08c?: `B ? 08c?: `B @ 08c?  : `B A 08c?  : `B B 0p?  B `B C 0Do?%B  F %Q B  D %Q B  E VA1?20%IQ `B F 08c?- `B G 08c?-r r`B H 0p?5b b`B I 08c?-R R`B J 08c?-B B`B K 08c?-2 2 `B L 08c?-" " `B M 08c?-  `B N 08c?: `B O 08c?: `B P 08c?: `B Q 08c?: `B R 08c?: `B S 08c?  : `B T 08c?  : `B U 0p?  B `B V 0Do?%B   W  `\L 8c 8c 1?  FRAM Cell ArrayUjB X@ BԔ?  ^B ! 61? & H  0޽h ? X(=^y___PPT10Y+D=' = @B +e9 L0 33+3@jj2(    C x \ 8c 8c1 ?3      C xD] 8c 8c1 ?p   l   j ,$D0`B  08c?hHh`B  08c?(H(`B  08c?Xp `B  08c?X`0`B  08c?hh`B   08c?((`B   08c?p8 `B   08c?`80`B   08c?8 h h`B   08c?8 ( (  Zaxaxa1?hJ: ? Row Address fB  68c? P`B  08c?H H `B  08c?P X `B  08c?h x `B  08c? @ `B  08c? H H   Zgxaxa1?H  7CASN (      `B  08c?0 0 `B  08c?8 ( `B  08c?8 x `B  08c? ( `B  08c? 0 0   Z8mxaxa1?0   7RAS`B  08c? 8 `B  08c? 8 `B  08c?H(  `B   08c?0 0  ! Zqxaxa1?h: ? Col Address `B " 08c?p( `B # 08c?`( 0`B $ 08c?H((`B % 08c?Hhh`B & 08c? ph `B ' 08c? `h 0`B ( 08c?x hh`B ) 08c?x ((`B * 08c?p `B + 08c?`0 , Zxxaxa1?g h : ? Row Address  - Z$}xaxa1?Wh: ? Col Address `B . 08c?p `B / 08c?`0`B 0 08c?((`B 1 08c?hh`B 2 08c?P  `B 3 08c?( 8 `B 4 08c?H@  `B 5 08c?H H `B 6 08c?hh`B 7 08c?((`B 8 08c?p( `B 9 08c?`(0`B : 08c?8hh`B ; 08c?8((fB = 68c? PfB > 68c? fB ? 68c?p pv B N8c))? XB C 08c? XB D 08c? ^B E 68c?P P ^B F 68c?P P h G  `4xaxa1?  8N rowsF  H `B I 08c?`B J 08c?fB K 68c?44fB LB 68c?44 M Zxaxa1? 8N colsXB N 08c? XB O 08c?XB P 08c?XB Q 08c?XB R 08c? S Z,xaxa1?' 8DRAMXB T 08c?X ^B U 68c? p ^B V 68c?  W Z\xaxa1?0Tr  > M bit planes d X <8c?x(^B Y 68c?(x(^B Z 68c?(8^B [ 68c?080^B \ 68c?8^B ] 68c?8^B ^ 68c?^B _ 68c?00XB ` 08c?X 8( a Zxaxa1?9  A Row Address   b Zxaxa1? I| DColumn Address^B c 68c?00`  d ZPxaxa1?(   @ M-bit Output XB e 08c?l    i  ,$D0 < Zxaxa1?  U z  b1st M-bit Access6  lB @ <8c?  A Zhxaxa1?   b2nd M-bit Access6 lB f <8c?p h lB g <8c?x @ x  h Zxaxa1? &  > Cycle Time H  0޽h ? X(=^___PPT10+D~' = @B D9' = @BA?%,( < +O%,( < +D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*j%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*i%(+fM  L0 q?i?p@y~P>(  v  N8c))?(HX8XB  08c? X  XB  08c?@P @^B  68c?H H^B  68c?(    `l£xaxa1?*@ * 8N rowsXB  08c?|LL,XB   08c?|,,,^B   68c?4^B  @ 68c?TT   ZDǣxaxa1?C"?c:5 8N colsXB   08c?XH(XB  08c?Xh(XB  08c?p`@XB  08c?``XB  08c?h  x  Zx̣xaxa1?xR 8DRAMXB  08c?   Z$xaxa1?8  DColumn Address^B  68c?h    Z8xaxa1? }  @ M-bit Output `z HP   HP ,$D0l  <8c?HXX `B  08c?h`B  08c?  `B  08c?hh `B  08c?` ` `B  08c?PpP fB  68c? XP fB  68c?P   Zأxaxa1?0   > M bit planes `B ! 08c?H8`B "B 08c?( # Zܣxaxa1?gr  D N x M SRAM XB $ 08c?0HX0XB % 08c?HXXB & 08c?hh8XB ' 08c?(h^B ( 6p?PP^B ) 68c?0X0 * Zxaxa1?(L A Row Address  ^B + 68c? , C x 8c 8c1 ?T     - C x 8c 8c1 ?   ^B t 68c?p@@^B u 68c?pp^ v Z 8c 8c1 ? ,$0 "After a row is read into the SRAM  register Only CAS is needed to access other M-bit words on that row RAS remains asserted while CAS is toggledH- qKe lK-e8c8Xl   } ,$D0fB / 68c?HfB 0 68c?`H`fB 1 68c?XXfB 2 68c?XhfB 3 68c?fB 4 68c?``fB 5 68c?8XfB 6 68c?8h 7  ` xaxa1?Jr ? Row Address lB 8 <8c? fB 9 68c? X fB : 68c?h fB ; 68c?fB < 68c?x (  =  `xaxa1? R 7CASfB ? 68c?8 ( fB @ 68c?8  A  ` xaxa1?0   7RASfB B 68c?  fB C 68c?(  fB D 68c?0 0  E  `Hxaxa1?r ? Col Address fB F 68c?H``fB G 68c?HfB H 68c?( XfB I 68c?( h J  `D xaxa1?  r ? Col Address fB K 68c?  XfB L 68c?  hfB M 68c?8 ` `fB N 68c?8  lB Q <8c?  R  `xaxa1?w r ? Col Address fB S 68c?XfB T 68c?hfB U 68c?( ``fB V 68c?(  W  `xaxa1?gr ? Col Address fB X 68c?XfB Y 68c?hfB Z 68c?``fB [ 68c?fB \ 68c?X fB ] 68c?  fB ^ 68c? x  lB _ <8c? fB ` 68c?H fB a 68c?fB b 68c?x lB c <8c? fB d 68c?8 fB e 68c?fB f 68c?x lB g <8c? fB h 68c?fB i 68c?``fB j 68c?  fB k 68c? ( fB l 68c?( 8 fB m 68c?8 H fB > 68c?0 0 l P   ~ 0 ,$D0 O  `,"xaxa1?  b1st M-bit Access6 rB P B8c?    n  ``(xaxa1?  \  [ 2nd M-bit6   o  `%xaxa1?   [ 3rd M-bit6   p  `$3xaxa1?   [ 4th M-bit6  rB q B8c? rB r B8c?  rB s B8c?  rB y B8c?    z  `\9xaxa1?z P "  > Cycle Time H  0޽h ? X(=^ } ___PPT10] .+V=D ' = @B D ' = @BA?%,( < +O%,( < +DT' =%(%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(Ds' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*v-%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*v-h%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*vh%(D' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*}%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*~%(+8+0+v +6 L0 55Dg@ 5(  v  N8c))?(HX8XB  08c? X  XB  08c?@` @^B  68c?H H^B  68c?(    `Ixaxa1?*@ * 8N rowsXB  08c?|LL,XB   08c?|,,,^B   68c?4^B  @ 68c?TT   Z@Nxaxa1?C"?c:5 8N colsXB   08c?XH(XB  08c?Xh(XB  08c?p`@XB  08c?``XB  08c?h  x  ZRxaxa1?xR 8DRAMXB  08c?   ZVxaxa1? q  DColumn Address^B  68c?h    Z[xaxa1? }  @ M-bit Output ,F HP   HP l  <8c?HXX `B  08c?h`B  08c?  `B  08c?hh `B  08c?` ` `B  08c?PpP fB  68c? XP fB  68c?P   Z(axaxa1?0   > M bit planes `B ! 08c?H8`B "B 08c?( # ZXexaxa1?gr  D N x M SRAM XB $ 08c?0HX0XB % 08c?HXXB & 08c?hh8XB ' 08c?(h^B ( 6p?PP^B ) 68c?00 * Zsxaxa1?(L A Row Address  ^B + 68c? , C xv 8c 8c1 ?T   ^B . 68c?p@@^B / 68c?ppl 0 ZD 8c 8c1 ?  k  BAfter a row is read into the SRAM register Inputs CAS as the starting  burst address along with a burst length Transfers a burst of data from a series of sequential addresses within that row A clock controls transfer of successive words in the burst  300MHz in 2004jA qK lKL -AL8c8Xd z <1?p0 ^B { 6D1?p 0 XB | 0D1?ppXB } 0D1?pXB ~ 0D1?XB  0D1?p^B  6D1?ppp  Zxaxa1?C"? 4+1^B 2 68c?a^B 3 68c?a^B 4 68c?A^B 5 68c?A^B 6 68c?Qq^B 7 68c?Qq^B 8 68c?^B 9 68c? :  `txaxa1? ? Row Address dB ; <8c? ^B < 68c? a ^B = 68c? Q@^B > 68c?@a@H @  `Dxaxa1?  7CAS^B A 68c?p q ^B B 68c? @  C  `xaxa1?h :  7RAS^B E 68c?` H ^B F 68c?` `h  G  `xaxa1?c  ? Col Address ^B H 68c?a ^B I 68c?a ^B J 68c?q ^B K 68c?q dB Q <8c? dB _ <8c? I I dB c <8c? dB g <8c? yy^B n 68c?h aah ^B  68c? @@^B  68c? `  p  `xaxa1?@ 9z   b1st M-bit Access6 jB q B8c?0  0  r  `xaxa1?@ Y   [ 2nd M-bit6   s  `xaxa1?@   [ 3rd M-bit6   t  `Dxaxa1?@ i  [ 4th M-bit6  jB u B8c?0 A 0 jB x B8c?@ a @  y  `xaxa1?P ` v "  > Cycle Time jB  B8c?0 0 jB  B8c?0 )0 XB  08c? XB  08c? XB  08c?XB  08c?XB  08c? XB  08c?   Z=xaxa1? <Row Add  H  0޽h ? X(=^___PPT10e.+D=' = @B +  L0 pDV(  r  S P`     c $*?P`P <$0  H  0޽h ? X(=^  ___PPT10 .pr++D3 ' = @B D ' = @BA?%,( < +O%,( < +D' =%(%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*5%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*5%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+ +> L0 /8'8PAN07(  0x 0 c $x6     0 s *D# P<$0  \5 P0  0 #"2&P0   z0 Bt1?0  L528c` x0 Bd1?  L628c` v0 B1?   L758c` t0 B1?`   M1258c` r0 B1?`  M1708c` p0 B1?  M2258c` n0 B1?P  xLatency (nsec) 8c` ;0 Bt1? 0 R16008c` :0 B1?  Q6408c` 90 B1?  Q2678c` 80 B%:1?`   Q1608c` 70 B.:1? `  P408c` 60 B/:1?  P138c` 50 BL9:1?P  s BWidth (MB/s)8c` 30 B4H:1?'0  L668c` 20 B::1?'  L548c` 10 BY:1? '  L208c` 00 Bb:1?` '  L188c` /0 Bk:1?'`  L168c` .0 B0]:1?'  L168c` -0 B}:1?P'  Q Pins/chip  8c` +0 B:1?A0' M2048c` *0 B:1?A' M1708c` )0 BX:1? A' M1308c` (0 B<:1?` A ' L708c` '0 B:1?A` ' L458c` &0 B:1?A' L358c` %0 Bܽ:1?PA' lDie size (mm2),  8c` #0 B:1?[0A M2568c` "0 B:1?[A L648c` !0 BD:1? [A L168c`  0 B:1?` [ A K18c` 0 BD:1?[` A N0.258c` 0 B:1?[A N0.068c` 0 BD:1?P[A OMb/chip8c` 0 Bt1?u0[ N20008c` 0 B81?u[ N19978c` 0 B1? u[ N19938c` 0 B1?` u [ N19868c` 0 B1?u` [ N19838c` 0 B1?u[ N19808c` 0 B1?Pu[ LYear8c` 0 B01?0u M64b8c` 0 B01?u M64b8c` 0 Bh01? u M64b8c` 0 BH01?`  u M32b8c` 0 B01?` u M16b8c` 0 B01?u M16b8c`  0 B01?Pu T Module Width  8c`  0 B01?0 S DDR SDRAM  8c`  0 B1? T Synch DRAM  8c`  0 BD1?  q FastPage DRAM8c` 0 B81?`   q FastPage DRAM8c` 0 B1?`  S Page DRAM  8c` 0 B81? NDRAM8c` 0 B1?P @8c``B =0 0o ?P0ZB >0 s *o ?P0ZB ?0 s *1 ?Pu0uZB @0 s *1 ?P[0[ZB A0 s *1 ?PA0AZB B0 s *1 ?P'0'ZB C0 s *1 ?P 0 `B D0 0o ?P 0 `B E0 0o ?PP ZB F0 s *o ? ZB G0 s *1 ? ZB H0 s *1 ?` ` ZB I0 s *1 ?  ZB J0 s *1 ? ZB K0 s *1 ? `B M0 0o ?00 ZB o0 s *1 ?P0 0 H1? 0   y!Patterson, CACM Vol 47, #10, 2004""H 0 0޽h ? X(=^$___PPT10.>v?+[W_D' = @B DS' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*0v%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*0v%(+8+0+0 + L0 D9(  d  <1?"   fpxaxaG 1 ?P  & @   `hxaxa1 ?P`     6   .  6F hh  .  6 @  .  6T8  .   68  .d   <1?   <x1? 5CPUdb   <1?pd   <1?  <1?  7Cached  <1? db  <1?   <1? `  8Memory  <L1?   5busd  <1?   Toxaxa1?0h GOne word wide organization (one word wide bus and one word wide memory)&HG7   `uxaxaG 1 ?`P` $D0`X___PPT9:2 Assume 1 clock cycle to send the address 25 clock cycles for DRAM cycle time, 8 clock cycles access time 1 clock cycle to return a word of data Memory-Bus to Cache bandwidth number of bytes accessed from memory and transferred to cache/CPU per clock cycle0qKZA0qKZA0qKZAR0lKZA;-R   @`  <1?0 ``  }#32-bit data & 32-bit addr per cycle$$ XB  0Do?0 `0 ^B  6D1?0 0   H1?@W =on-chipH  0޽h ? U>=UU(___PPT10++WDO' = @B D ' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+ +  L0   D (  d  <1?   `@zxaxa1 ?P`     6   .  6ԟF hh  .  6 @  .  6d8  .  6Ĥ8  .d   <1?   <1? 5CPUdb   <1?0d   <1?   <1?0 7Cached  <1?0  db  <1?0   <1? @  8Memory  <\1?0 5busd  <1?   `dxaxaG 1 ?p N$0qKZA  Hp1? =on-chip~  s *D@?  XB  0Do?  H  0޽h ? U>=UU(y___PPT10Y+D=' = @B + L0 =5E (   d   <1?    `xaxa1 ?P`      6   .   6$F hh  .   6 @  .   6d8  .   68  .d   <1?   <1? 5CPUdb   <1?0d   <1?   <1?0 7Cached   <1?0  db   <1?0    <1? @  8Memory   <<1?0 5busd   <1?    `DxaxaG 1 ?p N$0qKZA   HP1? =on-chip~   s * @?  XB   0Do?  R   ZS 8c 8c1 ? ,$D0  1 25 1 27 L0qKZA0lKU(8c8XM   Z\X 8c 8c1 ? 0 ,$D0  4/27 = 0.148L0qKZA 0lKU( 8c8XH   0޽h ? U>=UU(h`___PPT10@+D' = @B Do' = @BA?%,( < +O%,( < +D]' =%(D' =%(D' =A@BBBB0B@>%(D' =1:Bvisible*o3>+B#style.visibility<* %(+DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(+p+0+  ++0+  +  L0   E( (  (d ( <1? (  `xxaxa1 ?P`    ( 6{   . ( 6yF hh  . ( 6 @  . ( 68  . ( 6\8  .d  ( <1?  ( <̋1? 5CPUdb  ( <1?0d  ( <1?  ( <d1?0 7Cached ( <1?0  db ( <1?0  ( <1? @  8Memory ( < 1?0 5busd ( <1? (  `xaxaG 1 ?p N$0qKZA ( Hx1? =on-chip~ ( s *`  XB ( 0Do?P p H ( 0޽h ? U>=UU(y___PPT10Y+D=' = @B +  L0 @E%%0(  0d 0 <1? 0  `xaxa1 ?P`    0 6h   . 0 6F hh  . 0 6 @  . 0 68  . 0 6`8  .d  0 <1?  0 <1? 5CPUdb  0 <1?0d  0 <1?  0 <1?0 7Cached 0 <1?0  db 0 <1?0  0 <1? @  8Memory 0 <`1?0 5busd 0 <1? 0  `4xaxaG 1 ?p N$0qKZA 0 Hp1? =on-chip~ 0 s *`  XB 0 0Do?P p z @   0 @  ,$D0 0 B1?@ 0 0 Bx1?@P  = 25 cycles  f 0 61?P @  0 B1? P `  0 0 B }1?P `  = 25 cycles  f 0 61? `  0 B1?   0 0 B1?   = 25 cycles  f  0 61? `  !0 B1?@   0 "0 B0`1?   = 25 cycles  f #0 61?   $0 ZHa 8c 8c1 ?S0 ,$D0 R 1 4 x 25 = 100 1 102N0qKZA70lKU(78c8XW %0 Zc 8c 8c1 ? 0 ,$D0  (4 x 4)/102 = 0.157L0qKZA0lKU(8c8XH 0 0޽h ? U>=UU(___PPT10|+ND' = @B D' = @BA?%,( < +O%,( < +D]' =%(D' =%(D' =A@BBBB0B@>%(D' =1:Bvisible*o3>+B#style.visibility<*$0%(+D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*0%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%0%(+p+0+$0 ++0+%0 +  L0   `E8 (  8d 8 <1? 8  `4m:xaxa1 ?P`  :  8 6    . 8 6`F hh  . 8 6 @  . 8 68  . 8 68  .d  8 <1?  8 <1? 5CPUdb  8 <1?0d  8 <1?  8 <,1?0 7Cached 8 <1?0  db 8 <1?0  8 <01? @  8Memory 8 <1?0 5busd 8 <1? 8  `\xaxaG 1 ?p N$0qKZA 8 H1? =on-chip~ 8 s *8`j  XB 8 0Do? @ H 8 0޽h ? U>=UU(y___PPT10Y+D=' = @B +  L0 E%%@(  @d @ <1? @  `xaxa1 ?P`  :  @ 6   . @ 6F hh  . @ 6P @  . @ 68  . @ 68  .d  @ <1?  @ <1? 5CPUdb  @ <1?0d  @ <1?  @ <L1?0 7Cached @ <1?0  db @ <1?0  @ <1? @  8Memory @ <1?0 5busd @ <1? @  `xaxaG 1 ?p N$0qKZA @ H1? =on-chip~ @ s *`j  XB @ 0Do? @ z p`p  @ p`p ,$D0 @ B1?p 0  0 @ Bt1?  0  = 25 cycles  f @ 61? P 0  @ B1?0  0 @ BX1? p  <8 cycles  f @ 61?p   @ B1? P p  0 @ B1?pP   <8 cycles  f  @ 61? P   !@ B ğ1? p  0 "@ BƟ1?  p  <8 cycles  f #@ 61? `p  $@ Zԟ 8c 8c1 ?C0 ,$D0 R 1 25 + 3*8 = 49 1 51N0qKZA70lKU(78c8XS %@ Zʟ 8c 8c1 ? 0 `,$D0  (4 x 4)/51 = 0.314L0qKZA0lKU(8c8XH @ 0޽h ? U>=UU(___PPT10|+ND' = @B D' = @BA?%,( < +O%,( < +D]' =%(D' =%(D' =A@BBBB0B@>%(D' =1:Bvisible*o3>+B#style.visibility<*$@%(+D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*@%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%@%(+p+0+$@ ++0+%@ +X L0 g_EH (  H~ H s *P`  : + H Z`G 8c 8c1 ?@@e For a block size of four words cycle to send 1st address cycles to read DRAM cycles to return last data word total clock cycles miss penalty 0qKZA0lK_(0qKZA$ 8c8Xd H <1? H < 1? 5CPUdb H <1? d H <1? H <G1?0 7Cached  H <1?0 p db  H <1?0   H <K1? @T  ? Memory bank 1  H <pL1?  5busd  H <1? H HTS1? =on-chipd H <1?0 p  H <N1? 0T  ? Memory bank 0d H <1?0 p  H <<[1? PT  ? Memory bank 2d H <1?0  p  H <4_1? ` T  ? Memory bank 3T H B%(D' =1:Bvisible*o3>+B#style.visibility<*%P%(+D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*P%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*$P%(+p+0+$P ++0+%P +  EX6(  X~ X s *PP`   x X c $$@%  H X 0޽h ? X(=^y___PPT10Y+D=' = @B +0 }P?(  e  S ~ "hghg1 ? E  : Workstation Design Target: 25% of cost on Processor, 25% of cost on Memory (minimum memory size), rest on I/O devices, power supplies, box p   01 ?r   "H  0޽h ? X(=^0 f^p?(  d  c $r   "R  3 r"&e&e E  " TInstead, the memory system of a modern computer consists of a series of black boxes ranging from the fastest to the slowest. Besides variation in speed, these boxes also varies in size (smallest to biggest) and cost. What makes this kind of arrangement work is one of the most important principle in computer design. The principle of locality. The principle of locality states that programs access a relatively small portion of the address space at any instant of time. The design goal is to present the user with as much memory as is available in the cheapest technology (points to the disk). While by taking advantage of the principle of locality, we like to provide the user an average access speed that is very close to the speed that is offered by the fastest technology. (We will go over this slide in detail in the next lectures on caches). (UZ~ }H  0޽h ? X(=^h0 ( ?(    S ~"nana1 ? @  "     T1 ?    "H  0޽h ? a(p0 0(?(    S ~onana1 ? E  " JPut multiple words in one memory row  splits the decoder into two decoders (row and column) and makes the memory core square reducing the length of the bit lines (but increasing the length of the word lines). The lsb part of the address goes into the column decoder (e.g., 6 bits so that 64 words are assigned to one row (with 32 bits per word gives 2**11 bit line pairs) leaving 14 bits for the row decoder (giving 2**14 word lines) for an not quite square array. This scheme is good only for up to 64 Kb to 256 Kb. For bigger memories it is too SLOW because the word and bit lines are too long. SRAM allows you to read an entire row out at a time at a word. Each row control line is referred to as the word line and each vertical data line is referred to as the bit line.1p   01 ?s   oH  0޽h ? X(=^\0 ?(    S ~onana1 ? E  o 6"Similar to SRAM, DRAM is organized into rows and columns. But unlike SRAM, which allows you to read an entire row out at a time at a word, classical DRAM only allows you read out one-bit at time time. So we need several (planes) of them to store one word. The reason for this is to save power as well as area. Remember now the DRAM cell is very small we have a lot of them across horizontally. So it will be very difficult to build a Sense Amplifier for each column due to the area constraint not to mention having a sense amplifier per column will consume a lot of power. You select the bit you want to read or write by supplying a Row and then a Column address. Similar to SRAM, each row control line is referred to as the word line and each vertical data line is referred to as the bit line.p   01 ?s   oH  0޽h ? X(=^0 ~v @(  ^  S ~onana1 ? E  o bAnother performance booster for DRAM is fast page mode operation. In normal DRAM, we can only read and write M-bit at time because only one row and one column is selected at any time by the row and column address. 1) RAS 2) Latch 3) Cas 4) Latch 5) Data In other words, for each M-bit memory access, we have to provided a row address followed by a column address. Very time consuming. So the engineers get smart and say:  Wait a minute, this is silly, why don t we put a N x M register here so we can save an entire row internally whenever we access a row? Fp   01 ?s   oH  0޽h ? X(=^ 0 @8(    S ~3onana1 ? E  o So with this register in place, all we need to do is assert the RAS to latch in the row address, then entire row is read out and save into this register. After that, you only need to provide the column address and assert the CAS needs to access other M-bit within this same row. This type of operation where RAS remains asserted while CAS is toggled to bring in a new column address is called Page Mode operation. Store so don t have to repeat: SRAM + 2 = 71 min. (Y:51)p   01 ?s   oH  0޽h ? X(=^%0 f^C(  X  C s   o^  S :o E  o Memory baseline is a 64KB DRAM in 1980, with three years to the next generation until 1996 and then two years thereafter with a 7% per year performance improvement in latency. Processor assumes a 35% improvement per year until 1986, then a 55% until 2003, then 5% Need to supply an instruction and a data every clock cycle In 1980 there were no caches (and no need for them), by 1995 most systems had 2 level caches (e.g., 60% of the transistors on the Alpha 21164 were in the cache)H  0޽h ? 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MillsDavid L. Mills  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*,-./012456789:<=>?@ABIRoot EntrydO)PicturesE#Current User;SummaryInformation(+PowerPoint Document(1DocumentSummaryInformation83