ࡱ> za߿ߝXo( UUUUzag\Oy Ek( DDT$( / 0DTimes New RomanXX,y 0DArialNew RomanXX,y 0 DTahomaew RomanXX,y 0"0DWingdingsRomanXX,y 0@De0}fԚingsRomanXX,y 0PDMonotype SortsXX,y 0 A.@  @@``  @n?" dd@  @@`` <4x  -      DH/Xr$߿ߝXoifr$g\Oy Ekii AA1))?@8dg4KdKd 0ppp@ g43d3d 0ppp@  <4BdBd$l 0Xʚ;ʚ;<4!d!d$l 0$<4dddd$l 0$r0___PPT10 2___PPT9/ 0?`+4/11/97 6\course\cpeg323-05F\Topic7bO =`  How to Handle Read/Write`  One-word-line: (DEC 3100) Read: easy Send the address to the appropriate cache. The address comes either from the PC (for an instruction read) or from ALU (for an data access). If the cache signals hit, the requested word is available on the data lines. If the cache signals miss, we send the full address to the main memory. When the memory returns with the data, we write it into the cache.L%f```f`   Read Miss is easy to be handled quickly: read tag and read block can be done simultaneousely before we know it is a hit. Write is usually slower read tag and write block cannot be done simultaneousely. (Except: for one-word-line caches))P9$ )`P``9`$b@M  ]  &  For multiple-word-line: when write on a write miss, it is a read - modify - write cycle the original a portion write the block the tag comparison cannot be done in parallel, so it is slower4 ` ``    BWhy? Assume x, y map to the same set and cache has x initiallyC C` C    Assume before write, cache contain line x. when write y: a miss, and a write occurs, e.g.: write y.3 z Note after write miss, if not careful, we get But later a write back will destroy y1, y2, y4! \  2u \```b`/b6`     Write through (or store through) - The information is written to both the block in the cache and to the block in the lower-level memory. Write back (also called copy back) - The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. Write-back Clean and dirty blocks Dirty bit - indicate whether a line is modified while in the cache. When a  dirty line is replaced it must be written back to the main M.7x 2  x[ xH x `` `>``)` `` `` `[``C`     VThere are two options on a write miss: Write allocate (also called fetch on write) - The block is loaded, followed by the write-hit actions above. This is similar to a read miss. No write allocate (also called write around) - The block is modified in the lower level and not loaded into the cache. Think what you do when have a write miss!'  2 2* (````b``` `N`*` W   !When Write Through May Be Better?""` " When 2-level cache is used: CPU on chip small cache + a large off-chip cache Consistency is easier Memory traffic is avoid by the 2nd cachejxD x?x`#`` `?`   Write-back vs. Write-through`  Speed (write-back is fast) Traffic (in general, copy-back is better) If more than one read hit to the line So attractive to multiprocessor in this sense Cache consistency (write-through is better) Logic (copy-back more complicated)FTO`` ` ``` ` `T``` ` ``` ``   Write-back vs. Write-through`  PBuffering (4 is best for write-through) Needed for both, but copy-back only need 1. Management is complicated because when a ref is made, it must consult the buffer. Reliability (write-through is better) because main M has error detection  There is no clear choice in terms of performance ...) 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Dt  Rectangle: Click to edit Master text styles Second level Third level Fourth level Fifth level"%p0u   [#Click to edit Master subtitle style$$  Et 6! "``  j* c    Ft 6& "`   l*  c    Gt 60+ "`   l*  c   H t 0޽h ?/ >tBt @Eff؂o 0 P(    "  TdjJjJ ?\"   *b   H""DDff$  TvjJjJ ? "  *b   H""DDff(  ZwjJjJ ?\   *b   H""DDff*  ZjJjJ ?   *b   H""DDffp  01 ?&2  ?  Tgֳgֳ ? C  SClick to edit Master notes styles Second Level Third Level Fourth Level Fifth Level"    T H  0qi6Ɍ? ? a(80___PPT10.C PH0 (      T{jJjJ ?\"   *b   H""DDff"  TvjJjJ ? "  *b   H""DDff&  ZjJjJ ?\   *b   H""DDff(  Z$jJjJ ?   *b   H""DDffH  0qi6Ɍ? ? a(80___PPT10.zH 0L0 0(  r  S 87CtPp   H  0޽h ? 333gggk 0 (    Z,gֳgֳ ?0  Main Memory Update/Fetch Policy&! P!g( ! O  N gֳgֳ? S mUpdate : 8~16% are writes write-back may not touch main M at a write miss write-through higher traffic Fetch }0 K 0 %0uA0 0uA}0 K|0 Kc c%cc c cm  H  0޽h ? @Eff؂o  0 0((    # l gֳgֳ ??pP      # lgֳgֳ ?@p 0@  H  0޽h ? 333ggg  0 h`  (     # lgֳgֳ ?@pP  p  H  0޽h ? 333ggg  0 [S((  ( ( # lgֳgֳ ?@p0P   (  BCDEF1?< @Q;  (  BCDEF1?< @@;  (  BCDEF1?< @  ;  ( 3 r1))? 6   mblock8|0 nca  H ( 0޽h ? 333ggg  0 ;3,,0( ֳ 0 0 # l gֳgֳ ?@p 0P  8  |  ,0GpxB 0 H1?  xB 0 H1?!` xB 0 H1?!! xB 0 H1?a  a o@   i ~  0  i ~ xB 0 H1?" \ xB 0 H1? v ` v xB  0 H1? r xB  0 H1?f f r xB  0 H1? r   0 T'gֳgֳ? T~  Kxb    0 Tgֳgֳ? i z  ^x4,bj   0 TD.gֳgֳ? z z  ^x3,bj   0 T0gֳgֳ? ~  ^x2,bj   0 T4gֳgֳ? z  ^x1,bj  H@  s^ 0 s^xB 0 H1? xB 0 H1? VVxB 0 H1?RxB 0 H1?RxB 0 H1?  R 0 T``)` `` `` `[``C`     VThere are two options on a write miss: Write allocate (also called fetch on write) - The block is loaded, followed by the write-hit actions above. This is similar to a read miss. No write allocate (also called write around) - The block is modified in the lower level and not loaded into the cache. Think what you do when have a write miss!'  2 2* (````b``` `N`*` W   !When Write Through May Be Better?""` " When 2-level cache is used: CPU on chip small cache + a large off-chip cache Consistency is easier Memory traffic is avoid by the 2nd cachejxD x?x`#`` `?`   Write-back vs. Write-through`  Speed (write-back is fast) Traffic (in general, copy-back is better) If more than one read hit to the line So attractive to multiprocessor in this sense Cache consistency (write-through is better) Logic (copy-back more complicated)FTO`` ` ``` ` `T``` ` ``` ``   Write-back vs. Write-through`  PBuffering (4 is best for write-through) Needed for both, but copy-back only need 1. Management is complicated because when a ref is made, it must consult the buffer. Reliability (write-through is better) because main   !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~Root EntrydO)OZPicturesCurrent User JSummaryInformation(p7  T*@ܖ 0ܖDArialNew RomanTT*@ܖ 0ܖ DTahomaew RomanTT*@ܖ 0ܖ"0DWingdingsRomanTT*@ܖ 0ܖ@De0}fԚingsRomanTT*@ܖ 0ܖPDMonotype SortsTT*@ܖ 0ܖ A.@  @@``  @n?" dd@  @@`` <4x  -      DH/Xr$߿ߝXoifr$g\Oy Ekii AA1))?@8dg4KdKd@ 0ppp@ g43d3d@ 0ppp@  <4BdBd x 0Tʚ;ʚ;<4!d!d  x 0 <4dddd  x 0 r0___PPT10 2___PPT9/ 0?`+4/11/97 6\course\cpeg323-05F\Topic7bO = Update Policy`   How to Handle Read/Write`  One-word-line: (DEC 3100) Read: easy Send the address to the appropriate cache. The address comes either from the PC (for an instruction read) or from ALU (for an data access). If the cache signals hit, the requested word is available on the data lines. If the cache signals miss, we send the full address to the main memory. When the memory returns with the data, we write it into the cache.L%f```f`   Read Miss is easy to be handled quickly: read tag and read block can be done simultaneousely before we know it is a hit. Write is usually slower read tag and write block cannot be done simultaneousely. (Except: for one-word-line caches))P9$ )`P``9`$b@M  ]  &  For multiple-word-line: when write on a write miss, it is a read - modify - write cycle the original a portion write the block the tag comparison cannot be done in parallel, so it is slower4 ` ``    BWhy? Assume x, y map to the same set and cache has x initiallyC C` C    Assume before write, cache contain line x. when write y: a miss, and a write occurs, e.g.: write y.3 z Note after write miss, if not careful, we get But later a write back will destroy y1, y2, y4! \  2u \```b`/b6`     Write through (or store through) - The information is written to both the block in the cache and to the block in the lower-level memory. Write back (also called copy back) - The information is written only to the block in the cache. The modified cache block is written to main memory only when it is replaced. Write-back Clean and dirty blocks Dirty bit - indicate whether a line is modified while in the cache. When a  dirty line is replaced it must be written back to the main M.7x 2  x[ xH x `` `>``)` `` `` `[``C`     VThere are two options on a write miss: Write allocate (also called fetch on write) - The block is loaded, followed by the write-hit actions above. This is similar to a read miss. No write allocate (also called write around) - The block is modified in the lower level and not loaded into the cache. Think what you do when have a write miss!'  2 2* (````b``` `N`*` W   !When Write Through May Be Better?""` " When 2-level cache is used: CPU on chip small cache + a large off-chip cache Consistency is easier Memory traffic is avoid by the 2nd cachejxD x?x`#`` `?`   Write-back vs. Write-through`  Speed (write-back is fast) Traffic (in general, copy-back is better) If more than one read hit to the line So attractive to multiprocessor in this sense Cache consistency (write-through is better) Logic (copy-back more complicated)FTO`` ` ``` ` `T``` ` ``` ``   Write-back vs. Write-through`  PBuffering (4 is best for write-through) Needed for both, but copy-back only need 1. Management is complicated because when a ref is made, it must consult the buffer. Reliability (write-through is better) because main M has error detection  There is no clear choice in terms of performance ...) I 27  `` `` `` `1``` )   Write-back Write-through adv (1) fast, at the speed - easier to implement of cache memory - no write is necessary (2) less memory during a read miss traffic - consistency 2-   `  /4   0L0 0(  r  S 4CtPp   H  0޽h ? 333gggr{ W1$( Slide 5Slide 6Slide 7Slide 8Slide 9"When Write Through May Be Better?Write-back vs. Write-throughWrite-back vs. Write-through Slide 13  Fonts UsedDesign Template Slid&_o>David L. MillsDavid L. Millse Titles 4 $, ՜.+,0    mLetter Paper (8.5x11 in)>o   Times New RomanArialTahoma Wingdings 新細明體Monotype Sorts BlueprintUpdate PolicySlide 2How to Handle Read/WriteSlide 4Slide 5Slide 6Slide 7Slide 8Slide 9"When Write Through May Be Better?Write-back vs. Write-throughWrite-back vs. Write-through Slide 13  Fonts UsedDesign Template Slide Titles $_o> Guang R. GaoGuang R. GaoM has error detection  There is no clear choice in terms of performance ...) I 27  `` `` `` `1``` )   Write-back Write-through adv (1) fast, at the speed - easier to implement of cache memory - no write is necessary (2) less memory during a read miss traffic - consistency 2-   `  /4  r_>1Root EntrydO)NPicturesCurrent User DSummaryInformation(p7  PowerPoint Document(>DocumentSummaryInformation8H՜.+,D՜.+,    mLetter Paper (8.5x11 in)>o   Times New RomanArialTahoma Wingdings 新細明體Monotype Sorts BlueprintUpdate PolicySlide 2How to Handle Read/WriteSlide 4