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Sharing a resource by 2 or more instructions are done through multiplexing. f  " b -L "  "  bM   The symbol commonly used to represent an ALU. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder. The control lines labeled ALUOperation . Their values and the ALU operation are found in the next figure. Z E Q The values of the three ALU Control lines and the corresponding ALU operations.RR Instructions using ALU Load/store: address calculation - add Branch eq: subtract add/subtract R-type: and/or set-on-less-than need function code&6Z(&  8    GV#Features of MIPS Instruction Format$P$( #Features of MIPS Instruction Format$P$(The op field, also called the opcode, is always contained in bits 31-26. We will refer to this field as Op[5-0]. The two registers to be read are always specified by the rs and rt fields, at positions 25-21 and 20-16. This is true for the R-type instructions, branch equal, and for store. The base register for load and store instructions is always in bit positions 25-21 (rs). The 16-bit offset for branch equal, load, and store is always in positions 15-0. The destination register is in one of two places. For a load it is in bit positions 20-16 (rt), while for an R-type instruction it is in bit positions 15-11 (rd). Thus, we will need to add a multiplex or to select which field of the instruction is used to indicate the register number to be written. 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D| N Rectangle: Click to edit Master text styles Second level Third level Fourth level Fifth level"%p0u  N W#Click to edit Master subtitle style$ $ E| 6N "`` N D*   F| 6N "`  N F*   G| 6N "`  N F*  H | 0޽h ?/ >|B| @Eff؂o; 0 K(     TXڿ jJjJ ?08    p*  H""DDff  T jJjJ ?g 8   r*  H""DDff  Z jJjJ ?(0`    p*  H""DDff  Z jJjJ ?(g `   r*  H""DDffp  01 ?:^   ;  T gֳgֳ ? 6a   SClick to edit Master notes styles Second Level Third Level Fourth Level Fifth Level"     TH  0bf@? ? a(80___PPT10.\( @ H(     T jJjJ ?08    ^* H""DDff  T jJjJ ?g 8   `* H""DDff  Z0 jJjJ ?(0`    ^* H""DDff  Z3 jJjJ ?(g `   `* H""DDffH  0bf@? ? a(80___PPT10.\`=A 0 h`0(    # lNgֳgֳ ?C|X  N H  0޽h ? 333gggy___PPT10Y+D='  = @B +  0 0t6(  tx t c $JT?x  T ~ t s *hKT@x,L\  T H t 0޽h ? 333gggy___PPT10Y+D='  = @B +  0 0(P( Dtg   # lH[Tgֳgֳ ??x\,  T   # l \Tgֳgֳ ?@x4  T H  0޽h ? 333ggg  0 0(`( ֳ   # lHiTgֳgֳ ??x h  T   # l jTgֳgֳ ?@x  T H  0޽h ? 333ggg> 0 P~(  8 7  7 l  <7c? l  <7c?+l  <7c?4  l  <7c?4Rb x  HG7c? MNmrR  BZG/*7c? i0`  0? j ?   T`Tgֳgֳ?xL 4PCrB   B7c?rB   B7c?6*   T̋Tgֳgֳ?e79 ; Instruction    T|Ngֳgֳ?u HInstruction memoryP   BBCDEF7c?AA @5Bw rB  B7c?`%rB  B7c?  rB  B7c?  rB  B7c?2I& IrB  B7c?2a& a  TTgֳgֳ?/ _  j8Data Register # Registers Register # Register #9Z9  TTgֳgֳ?;z: 5ALU  T Tgֳgֳ?Yb  r*Address Data Memory Data,+P   B/CDE F7c?.@ -    B CTDEF 7c? S S @47rB  B7c?rB  B7c??>  TܞTgֳgֳ? 9< An abstract view of the implementation of the MIPS subset showing the major functional units and the major connections between them.PH  0޽h ? 333ggg  0 6.p (     # lTgֳgֳ ??xP  T   3 rxTgֳgֳ ?@x\P| T H  0޽h ? 333gggy 0 )!`$ (  $H 8    $  l $ <7c?qrB $ B7c? zz $ TlTgֳgֳ?}c ; Instruction  $ TȿTgֳgֳ? HInstruction memoryP $ TTgֳgֳ?'W GInstruction addressPrB $ B7c?w<x $ HG7c?HrR  $ BZG/*7c?9b`  $ 0?<q  $ TTgֳgֳ? l E ALU Sum rB  $ B7c?rB  $ B7c?~CrB $ B7c?El $ <7c? x  $ TpTgֳgֳ?w U ) 4PCrB $ B7c?~ C rB $ B7c?  xB $ H7c?   $ TTgֳgֳ? <  5Write $ TTgֳgֳ?A   d4a. Instruction memory b. Program counter c. Adder551 $ N Tgֳgֳ? 2 Two state elements are needed to store and access instructions, and an adder is needed to compute the next instruction address.PH $ 0޽h ? 333ggg  0   p(D (  ( 8 K>  (K> l ( <7c?   ( TTgֳgֳ?m   ; Instruction  ( TTgֳgֳ?r W J  HInstruction memoryP ( TTgֳgֳ?   > Read address P rB ( B7c? z l ( <7c?9  ( TTgֳgֳ?x 4PCrB  ( B7c? v x  ( HG7c? FrR  ( BZG/*7c? a`  ( 0?    ( TTgֳgֳ?3t 5Add (  B CDEF 7c? @ @ @K>  (  BCCDE F7c?B@R rB ( B7c?~ q q ( TTgֳgֳ?   149 ( T0Tgֳgֳ? d _A portion of the datapath used for fetching instructions and incrementing the program counter.`P`GH ( 0޽h ? 333ggg 0 ;3&&,( @H , , Ttgֳgֳ?   ]The two elements needed to implement R-format ALU operation are the register file and the ALU^P^v8 'B  &,'B @ B  ,Bx , HG7c?r rR , BZG/*7c?c ` , 0?(f , Ttgֳgֳ? 5ALUrB , B7c?iirB , B7c?\m\rB  , B7c?`o`  , TL tgֳgֳ?> < ALU result F xB  , H7c?==  , T4tgֳgֳ?%B = ALU operationY @ |'!  ,|'! l , <7c?'  , Ttgֳgֳ?-u I ; Registers  , Tptgֳgֳ? I][ ARead register 1FrB , B7c? 0! 0rB , B7c?| , Tttgֳgֳ?Y   = Read data 1 F  , TT!tgֳgֳ? ] ARead register 2F , Ttgֳgֳ?  BWrite register F , T(tgֳgֳ? u < Write Data F  , T'tgֳgֳ?R   = Read data 2 F rB , B7c? i irB , B7c?rB , B7c?rB , B7c? , T/tgֳgֳ?   X( a. Registers b. ALU)) , T3tgֳgֳ?| BRegister numbersP ,  BFCDEF7c?EE @|xB  , H7c? !, T8tgֳgֳ?K{; 4Data ",  BFCzDEF7c?EyEy @xB #, H7c?xB $, H7c?K  %, T(=tgֳgֳ?u p  5WriteH , 0޽h ? 333ggg 0 tl0( k>s0$ 08 .^A  0^.A l 0 <7c?k^  0 TBtgֳgֳ?  ; Registers  0 TpGtgֳgֳ?y  ARead register 1FrB 0 B7c?  0 T(Ktgֳgֳ? L  = Read data 1 F  0 TOtgֳgֳ?y  ARead register 2F 0 TTtgֳgֳ?yU  BWrite register F  0 TCDEF7c?== @)g 0 Tktgֳgֳ?cK ; Instruction  0 Tptgֳgֳ?] EJ}  w#The datapath for R-type instruction$$H 0 0޽h ? 333gggb 0  4(  4 L .7  4# .7 l 4 <7c?y P 4 Tvtgֳgֳ?x A Data memory P  4 Ttztgֳgֳ?{" > Read address F rB 4 B7c?  rB 4 B7c?lwn 4 Ttgֳgֳ?#1  ; Read data F  4 T0tgֳgֳ?nb ? Write addressF  4 Ttgֳgֳ? < Write Data F rB  4 B7c?zCCrB  4 B7c? CCrB  4 B7c?;;rB  4 B7c?xB 4 H7c?^  4 THtgֳgֳ?w7  4Readl2 4 <7c?ih^ 4 Ttgֳgֳ?\ A Sign extend P xB 4 H7c?  xB 4 H7c??xB 4 H7c?. 4 Txtgֳgֳ?7 5Write 4 Ztgֳgֳ? K)  \,a. Data memory unit b. Sign-extension unit--I 4 T0tgֳgֳ? ^ The two units needed to implement loads and stores are the data memory unit and the sign-extension unit, in addition to the register file and ALUP 4 Zhtgֳgֳ?+  216 4 Z@tgֳgֳ?QE 232H 4 0޽h ? 333ggg5 0 **8u( u>s0`T  8!8  g3  )8g 3  8  B}CDDEF 7c?7CC| @@ 7 rB 8 B7c?7 7 rB 8 B7c?0zxB 8 H7c? Y{ xB 8 H7c? \ { l 8 <7c?bz 8 Ttgֳgֳ? A Data memory P   8 Txtgֳgֳ? > Read address F xB  8 H7c?,C  8 TԲtgֳgֳ?@| ; Read data F   8 Ttgֳgֳ?]o ? Write addressF  8 T tgֳgֳ?K  < Write Data F rB 8 B7c?X @   8 x 8 HG7c? C rR 8 BZG/*7c? 3 ` 8 0?   8 Ttgֳgֳ? g  5ALUrB 8 B7c?U  8 Ttgֳgֳ?0 m c < ALU result F  8 Ttgֳgֳ?:  , 6ZeroFl 8 <7c?}g 8 TLtgֳgֳ?i ; Registers  8 Ttgֳgֳ? ARead register 1F 8 Ttgֳgֳ?7  = Read data 1 F  8 Ttgֳgֳ? ARead register 2F 8 Ttgֳgֳ?5 BWrite register F 8 Tltgֳgֳ?z! < Write Data F  8 T(tgֳgֳ?0  = Read data 2 F rB 8 B7c?@).rB  8 B7c?M M !8  BCDEF7c? @ "8  BgCDEF 7c?ff_ @3  #8 Ttgֳgֳ?  216 $8 Ttgֳgֳ?  232f2 %8 67c?V  &8 T tgֳgֳ?   A Sign extend P  '8  BCDEF7c? @pm (8 Ttgֳgֳ? Oe ; Instruction  *8 TDtgֳgֳ? [ <The datapath for a load or store that does a register access==1H 8 0޽h ? 333gggA 0 ++<(  <X8 7p   *<p7  l < <7c?| l < T gֳgֳ? | ; Registers  < T4 gֳgֳ? ARead register 1F < T gֳgֳ?O   = Read data 1 F  < T gֳgֳ? ARead register 2F < TT gֳgֳ?@ BWrite register F < Tl gֳgֳ?t < Write Data F   < T gֳgֳ?a   = Read data 2 F x  < HG7c?$u~ArR  < BZG/*7c?#`  < 0?t3  < T gֳgֳ?H 7AdderrB < B7c?A < Th! gֳgֳ?RF 5SumFx < HG7c?$~hrR < BZG/*7c?K` < 0?Z < T% gֳgֳ?ai 5ALUrB < B7c?K < T) gֳgֳ?|[ 6ZeroFrB < B7c? xB < H7c?! gq xB < H7c? B q  < T- gֳgֳ?   216 < T1 gֳgֳ?  232l2 < <7c?   < T gֳgֳ? A 7 B Shift left 2 F  <  BCVDEF 7c?qqUU @  f2 < 67c?@ |  < T9 gֳgֳ?  A Sign extend P rB  < B7c?   !< T\> gֳgֳ?pE0 r PC + 4 from instruction datapath!!rB "< B7c? 1 #< TA gֳgֳ?8 \ = Branch target $< TE gֳgֳ?Yx ITo branch control logicFrB %< B7c? rB &< B7c? %rB '< B7c?=y?xB (< H7c?7 )< TJ gֳgֳ?a ; Instruction  +< TO gֳgֳ? S e The datapath for a branch uses an ALU for evaluation of the branch condition and a separate adder for computing the branch target as the sum of the incremented PC and the sign-extended, lower 16 bits of the I instruction (the branch displacement) shifted left 2 bits.PH < 0޽h ? 333ggg   0 0(@(  @ @ # lW gֳgֳ ??x    @ # llX gֳgֳ ?@x5    H @ 0޽h ? 333gggy___PPT10Y+D='  = @B + 0 .&D( ֳ D4 D  `N1))?% I+ PCombining the datapaths for the memory instructions and the R-type instructionsQQ :J D C "A 5-11 l H D 0޽h ? 333gggy___PPT10Y+D='  = @B +D 0 kcH(  HJ H C "A 5-12 q H  fg 1))? X sThe instruction fetch portion of the datapath is appended to the datapath that handles memory and ALU instructions.tZt,%+H H 0޽h ? 333gggy___PPT10Y+D='  = @B +- 0 TLL(  LJ L C "A 5-13 Z L  f0p 1))?  nThe simple datapath for the MIPS architecture combines the elements required by different instruction classes.oZo \H L 0޽h ? 333gggy___PPT10Y+D='  = @B +   0   P> (  P P # lv gֳgֳ ?@x'    o 8 Ow  POw A@ Ow  POw x P HG7c?[  rR P BZG/*7c?L  ` P 0? O rB P B7c? z rB P B7c? Q rB P B7c? 9T :  P Tz gֳgֳ?   5ALUrB  P B7c?    P T$ gֳgֳ?  v = ALU operationrB  P B7c? S SrB  P B7c? |  P T| gֳgֳ?V {w2 FZero Result Overflow_rB P B7c?   P T gֳgֳ?O 9a b] P T gֳgֳ? # 9  RCarryOut  P TD gֳgֳ?y  C ALU Control (H P 0޽h ? 333gggy___PPT10Y+D='  = @B +  0  TZ(  T T # l gֳgֳ ?@x i   d T <7c?a  T T( gֳgֳ? S  ALU Control lines Function 000 And 001 Or 010 Add 110 Subtract 111 Set-on-less-than ,pB T H7c?pB T H1?| | pB T H1?pB T H1?pB  T H1?pB  T H1?@ @ a   T T gֳgֳ?:! @ cont d  T T gֳgֳ?y  C ALU Control (H T 0޽h ? 333gggy___PPT10Y+D='  = @B +; 0 bZX(  X X NA ?? X $ 0 0h X N侳 gֳgֳ?@ e-  This table shows how the ALU control bits are set depending on the ALUOp control bits and the different function codes for the R-type instruction. CMl X Tij gֳgֳ?  `The opcode, listed in the first column, determines the setting of the ALUOp bits. All the encoding are shown in binary. Notice that when the ALUOp code is 00 or 01, the output fields do not depend on the function code field; in this case, we say that we  don t care about the value of the function code, and the function field is shown as XXXXXX. When the ALUOp value is 10, the function code is used to set the ALU control input.P<BFH X 0޽h ? 333gggy___PPT10Y+D='  = @B +=  0 d\\(  \ \ # lϳ gֳgֳ ?@x+K     \  B_CbDEF1?^"aVa @n g H \ 0޽h ? 333gggy___PPT10Y+D='  = @B + 0 `t(  ` ` NA ??yX $ 0 0: ` N gֳgֳ?L $  fThe truth table for the three ALU control bits as a function of the ALUOp and function code field. gZgDL ` T\ gֳgֳ? J RSome don t care entries have been added. For example, the ALUOp does not use the encoding 11, so the truth table can contain entries 1X, and X1 rather than 10 and 01..8Z:k ` T gֳgֳ? DALU Control Design H ` 0޽h ? 333gggy___PPT10Y+D='  = @B +  0  88dB( 35, dj d BG@87c? ^2 d 67c?] FX d 0?, +j d BG7c?s l 0X d 0?" IpB d H7c? 5j d BG@87c?= ^2  d 67c? TX  d 0? j  d BG@87c? d ^2  d 67c?w  X  d 0?: 9 j d BG7c?q ~ w X d 0?Y = pB d H7c?t pB d H7c? < d  B*CDEF7c?)) @8v  pB d H7c?pB d H7c?I  J  d  B@CwDEF 7c??oov/v @5  d  B CIDEF7c? HH @CM d  BCDEF7c? @ d d <7c?9k  d  BC<DEF7c?;X;X @ jB d B7c? d  BCDEF7c? @?;pB d H7c?A ApB d H7c?jB d B7c?% d TH gֳgֳ? QALUOp  d TA gֳgֳ? A 8ALUOp0 !d T D gֳgֳ?P  8ALUOp1 "d TH gֳgֳ?P = Operation 2  #d TdL gֳgֳ?_   = Operation 0  $d Tl gֳgֳ? = Operation 1 jB %d B7c? &d TP gֳgֳ?Y < Operation  pB 'd@ H7c? C^2 (d 67c?^2 )d 67c?^2 *d 67c?2  M^2 +d 67c?,G^2 ,d 67c?^2 -d 67c?r ^2 .d 67c?:U^2 /d 67c?Z u ^2 0d 67c?^2 1d 67c?^2 2d 67c?t5^2 3d 67c??#>Z 4d T|X gֳgֳ? 9F (5-0) 5d Tt\ gֳgֳ?~  EF3 F2 F1 F0rpB 6d H7c?    7d T`a gֳgֳ?^  CALU control block? 8d Te gֳgֳ?  gThe ALU control block generates the three ALU control bits, based on the function code and ALUOp bits.hh\H d 0޽h ? 333gggy___PPT10Y+D='  = @B +0  0 WOch( `쎈 h h # li gֳgֳ ??xv    Oh  `1))? Qh l gֳgֳ ?Rectangle: Click to edit Master text styles Second level Third level Fourth level Fifth levely8 Field 0 rs rt rd shamt funct Bit positions 31-26 25-21 20-16 15-11 10-6 5-0 a. R-type instructionx wn0 wn$ wnP  d Rh <7c?{vB Sh N7c?llvB Th N7c? vB Uh N7c?\\vB Vh N7c?88vB Wh N7c?   Xh N gֳgֳ?Yr  QField 35 or 43 rs rt address Bit positions 31-26 25-21 20-16 10-6 b. Load or store instructionHx 0+ ,d Yh <7c?St vB Zh N7c?Kee vB [h N7c?O  vB \h N7c?S !  ]h Nt gֳgֳ? |L =Field 4 rs rt address Bit positions 31-26 25-21 20-16 15-0 c. branch instructionHk 0$ , d ^h <7c? ~ vB _h N7c? oo vB `h N7c? vB ah N7c?   H h 0޽h ? 333gggy___PPT10Y+D='  = @B +n  0 l(  l l 3 r gֳgֳ ?@x\h    l T gֳgֳ?U > cont d l s  gֳgֳ ??xv   H l 0޽h ? 333gggG 0 FF kkpUF(  ppB p H1?iC8   ip  p  B~CtDEF7c?ss} @m W x p HG7c?;?rR p BZG/*7c?2L\` p 0?7/rB p B7c?0 p TH gֳgֳ?)d5 5ALU xB  p H7c? C@  57 p 57x  p HG7c?+ 5rR  p BZG/*7c? B `  p 0? -   p TĹ gֳgֳ? [ 5Add  p TLȹ gֳgֳ?#=7 < ALU result F  @ d pdr p BG7c?X p Tй gֳgֳ?d  0 M u x 1bFFF   rB p B7c?n p  BZCDE F7c?Y@Y Y@ b?w  pb?w l p <7c??-  p T(ӹ gֳgֳ?bu > Read address F   p Tѹ gֳgֳ?i; _Instructin memoryF   p Tɹ gֳgֳ?ow! DInstruction (31-0)F @ 0 p0l p <7c?0 p Th gֳgֳ? 2PC  p  B'CmDEF 7c?Sll&& @)rB p B7c?(( p  B"CDE F7c?!@ /)  p TD gֳgֳ?Cw 14 l !p <7c??m   "p T gֳgֳ?a, /  n<Read register 1 Read register 2 Write register Write data=F=  #p T gֳgֳ?v  F KRead data 1 Read data 2F @ s+  &ps+ r $p BG7c?~  %p TD gֳgֳ?s+   0 M u x 1bFFF   f2 'p 67c? {  (p T gֳgֳ?k U ;  ? Sign extend   @    +p  l2 )p <7c?   *p T4 gֳgֳ?  = ALU control   l ,p <7c?juD  -p T gֳgֳ?Fy  ]+Read address Write address Write data,F,  .p T gֳgֳ?C K ; Read data F   /p T gֳgֳ?=/   A Data memory F  x 0p HG7c?^ P* rR 1p BZG/*7c?J ] ` 2p 0? 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Gao4 $, heet Excel.Sheet.802Microsoft Excel WorksheetWorksheet Excel.Sheet.802Microsoft Excel Worksheetn/ 0|DTimes New RomanTTyܖ 0ܖDTahomaew RomanTTyܖ 0ܖ" DWingdingsRomanTTyܖ 0ܖ0DArialngsRomanTTyܖ 0ܖ@De0}fԚngsRomanTTyܖ 0ܖ A.@  @@``  @n?" dd@  @@`` D<"'  + ,  9dlDH 42$` K(]+2$*NOs'N4Qr$߿ߝXoif b$4 lY#d|e b$9oJ A#P@ɇb$4Ƒ 6] r$g\Oy Eki?w AA1))?@8!"/g4KdKdą 0ppp@  <4BdBd l 0Tʚ;ʚ;<4!d!d l 0 <4dddd l 0 0___PPT10 l___PPT9Nnu=!BWk@~PNG  IHDRF} PLTE3:tRNS@f cmPPJCmp0712Om9IDATc``b $<&40(Zжj˂AtM iIENDB`/ 0X4.N ?X+ D\course\cpeg323-05F\Topic5-323.pptO =;Topic 5: Processor Architecture Implementation Methodology<x<  4 Reading List (WSlides: Topic5x Henn & Patt: Chapter 5 Other papers as assigned in class or homework 6W " W,<#5ABET Outcomes `   Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) Ability to use the techniques, skills and modern engineering tools necessary for engineering practice Knowledge of related topics in computer science disciplinePb  Outline(zAn overview Datapath building blocks Implementation of a simple (single-cycle) datapath A multiple cycle implementation{ " {, <" Overview (The basic instruction execution flow Some conventions 32 bit datapath clocking strategy (edge-triggered) We focus on a subset of MIPS Memory-reference instructions: lw, sw ALU ops: add, sub, and, or Branch equal instructions (beq) and the jump instruction (J)|6 " 3 - " ~ -63~P=`7  Datapath Components( YCommon to all instructions: Instruction memory PC and its update Datapath of R-R type instructions ALU Register set Datapath of memory-reference instructions ALU (for address calculation) Register set Sign extension unit data memory Datapath for a branch inst. (e.g. beq $1, $2, offset) Sign extension + 2bit shifter Reg Adder ALU (zero output) " F% -F" " F -F* " FK -F6  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~ " F: -F%"*K6  :bB+m/ 3     ,A Simple (one-cycle) Datapath Implementation-P-(One-cycle: No resource can be used more than once by an instruction If used more than once ==> duplicate it! Sharing a resource by 2 or more instructions are done through multiplexing. f  " b -L "  "  bM PowerPoint Document(ΦDocumentSummaryInformation80Worksheet Excel.Sheet.802Microsoft Excel WorksheetWorksheet Excel.Sheet.802Microsoft Excel Worksheet"/ 00DTimes New RomanTTyܖ 0ܖDTahomaew RomanTTyܖ 0ܖ" DWingdingsRomanTTyܖ 0ܖ0DArialngsRomanTTyܖ 0ܖ A.@  @@``  @n?" dd@  @@`` <4!'  + ,  9dlDH42$` K(]+2$*NOs'N4Qr$߿ߝXoif b$4 lY#d|e b$9oJ A#P@ɇb$4Ƒ 6] r$g\Oy Eki?w AA1))?@8!"/g4KdKd 0ppp@  <4BdBd x 0Tʚ;ʚ;<4!d!d  x 0 <4dddd  x 0 0___PPT10 l___PPT9Nnu=!BWk@~PNG  IHDRF} PLTE3:tRNS@f cmPPJCmp0712Om9IDATc``b $<&40(Zжj˂AtM iIENDB`/ 0X4.N ?X+ D\course\cpeg323-04F\Topic5-323.pptO =;Topic 5: Processor Architecture Implementation Methodology<x<  4 Reading List (WSlides: Topic5x Henn & Patt: Chapter 5 Other papers as assigned in class or homework 6W " W,<Outline(zAn overview Datapath building blocks Implementation of a simple (single-cycle) datapath A multiple cycle implementation{ " {, <" Overview (The basic instruction execution flow Some conventions 32 bit datapath clocking strategy (edge-triggered) We focus on a subset of MIPS Memory-reference instructions: lw, sw ALU ops: add, sub, and, or Branch equal   The symbol commonly used to represent an ALU. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder. The control lines labeled ALUOperation . Their values and the ALU operation are found in the next figure. Z E Q The values of the three ALU Control lines and the correspinstructions (beq) and the jump instruction (J)|6 " 3 - " ~ -63~P=`7  Datapath Components( YCommon to all instructions: Instruction memory PC and its update Datapath of R-R type instructions ALU Register set Datapath of memory-reference instructions ALU (for address calculation) Register set Sign extension unit data memory Datapath for a branch inst. (e.g. beq $1, $2, offset) Sign extension + 2bit shifter Reg Adder ALU (zero output) " F% -F" " F -F* " FK -F6 " F: -F%"*K6  :bB+m/ 3     ,A Simple (one-cycle) Datapath Implementation-P-(One-cycle: No resource can be used more than once by an instruction If used more than once ==> duplicate it! Sharing a resource by 2 or more instructions are done through multiplexing. f  " b -L "  "  bM   The symbol commonly used to represent an ALU. This symbol is also used to represent an adder, so it is normally labeled either with ALU or Adder. The control lines labeled ALUOperation . Their values and the ALU operation are found in the next figure. Z E Q The values of the three ALU Control lines and the corresponding ALU operations.RR Instructions using ALU Load/store: address calculation - add Branch eq: subtract add/subtract R-type: and/or set-on-less-than need function code&6Z(&  8    GV#Features of MIPS Instruction Format$P$( #Features of MIPS Instruction Format$P$(The op field, also called the opcode, is always contained in bits 31-26. We will refer to this field as Op[5-0]. The two registers to be read are always specified by the rs and rt fields, at positions 25-21 and 20-16. This is true for the R-type instructions, branch equal, and for store. The base register for load and store instructions is always in bit positions 25-21 (rs). The 16-bit offset for branch equal, load, and store is always in positions 15-0. The destination register is in one of two places. For a load it is in bit positions 20-16 (rt), while for an R-type instruction it is in bit positions 15-11 (rd). Thus, we will need to add a multiplex or to select which field of the instruction is used to indicate the register number to be written. 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The two registers to be read are always specified by the rs and rt fields, at positions 25-21 and 20-16. This is true for the R-type instructions, branch equal, and for store. The base register for load and store instructions is always in bit positions 25-21 (rs). The 16-bit offset for branch equal, load, and store is always in positions 15-0. The destination register is in one of two places. For a load it is in bit positions 20-16 (rt), while for an R-type instruction it is in bit positions 15-11 (rd). Thus, we will need to add a multiplex or to select which field of the instruction is used to indicate the register number to be written. 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