ࡱ> 79GH8za߿ߝXo( UUUUzag\Oy Ek( DD |( n/ 0|DTimes New RomanTTyܖ 0ܖDTahomaew RomanTTyܖ 0ܖ" DWingdingsRomanTTyܖ 0ܖ0DArialngsRomanTTyܖ 0ܖ@DSymbolgsRomanTTyܖ 0ܖ A.@  @@``  @n?" dd@  @@`` 0(<O0$34$;  LD2H     '"!!"#$%&'"()+/+,..L015O$$r$߿ߝXoifr$g\Oy Ekii AA1))?@8^_ g4KdKdą 0ppp@  <4KdKd l 0T@ ʚ;ʚ;<4!d!d l 0 <4dddd l 0 0___PPT10 ___PPT9nu=!BWk@~PNG  IHDRF} PLTE3:tRNS@f cmPPJCmp0712Om9IDATc``b $<&40(Zжj˂AtM iIENDB`/ 02367:=>.?*@DE>F,K.LQSTUVWXYZ[\]^H_.`adb.c?X+ D\course\cpeg323-05F\Topic2-323.pptO =h&&Topic II Instruction-Set Architecture'P'CIntroduction A Case Study: The MIPS Instruction-Set Architecture 6A " A' Reading List (WSlides: Topic2x Henn & Patt: Chapter 2 Other papers as assigned in class or homeworks 4W " W>1 `2The Stored Memory ComputerP$Five parts of a computer Datapath (channels/changes bits) Control (directs operations) Memory (places to keep bits) Input (get data from outside) Output (send data to outside , "  " a3!Steps in Executing an Instruction"P"(Instruction Fetch: Fetch the next instruction from memory Instruction Decode: Examine instruction to determine: What operation is performed by the instruction (e.g., addition) What operands are required, and where the result goes Operand Fetch: Fetch the operands Execution: Perform the operation on the operands Result Writeback: Write the result to the specified location Next Instruction: Determine where to get next instruction p " v "  " )  (-*@ hb5What is Specified in an ISA?P(2Instruction Decode: How are operations and operands specified? Operand Fetch: Where can operands be located? How many? Execution: What operations can be performed? What data types and sizes? Result Writeback: Where can results be written? How many? Next Instruction: How can we choose the next instruction?3x- + ?** dc6A Simple ISA: Memory-Memory(EWhat operation becan performed? Basic arithmetic (for now) What data types and sizes? 32-bit integers Where can operands and results be located? Memory How many operands and results ? 2 operands, 1 result How are operations and operands specified? OP DEST, SRC1, SRC2 How can we choose the next instruction? Next in sequence  "  " 9 "  + +   (2d7 Memory Model (lThink of memory as being a large array of n integers, referenced by the index (random Access Memory, or RAM).m " nl e8Simple Code Translation( Given the C code A = B + C; we could decide that variable A uses location 100, B uses 48, and C uses 76. Convert the code above to the following  assembly code: ADD M[100], M[48], M[76] How would we express A = (B + C) * (D + E);Zf9Using a Temporary Location&( Assume we put A in 100, B in 48, C in 76, D in 20, and E in 32. Now choose an unused memory location (e.g., 84). ADD M[100], M[48], M[76] # A = B + C ADD M[84], M[20], M[32] # temp = D + E MUL M[100], M[100], M[84] # A = A * temp g: Problems with Memory-Memory ISAs!P!(CMain memory much slower than arithmetic circuits This was as true in 1950 as in 2003! It takes a lot of room to specify memory addresses Results are often used one or two instructions later Remember: make the common case fast! Solution: store temporary or intermediate results in fast memories near the arithmetic units. 1 " x% -xi " x% " x " (^ " x -x1%sCh;Accumulator Machines&(0 An  accumulator machine keeps a single high-speed buffer (e.g., a set of D latches or flip-flops, one for each data bit) near the arithmetic logic. In the simplest kind, only one operand can be specified; the accumulator is implicit:  OP operand means: acc. = acc. OP operand Example: LOAD M[48] # Load B into acc. ADD M[76] # Add C to acc. (now has B+C) STORE M[100] # Write acc. To APx(x (oi<'Accumulator Machines Does A=(B+C)*(D+E)&((  LOAD M[20] # Load D into acc. ADD M[32] # Add E to acc. (now has D+E) STORE M[100] # Write acc. To A LOAD M[48] # Load B into acc. ADD M[76] # Add C to acc. (now has B+C) MUL M[100] # Multiply A to acc. STORE M[100] # Write (B+C) * (D+E) to A x j=$Shortcomings of Accumulator Machines%P%$Still requires storing lots of temporary and intermediate values in memory Accumulator only really beneficial for a chain (sequence) of calculations where the result of one is the input to the next.  " Zk>:Still, Accumulator Machines Were Common in Early Computers;P;(A simple design, and hence popular, especially for Early computers Early microprocessors (4004, 8008) Low-end (cheap) models Reason: accumulator logic much more expensive than memory Vacuum tubes vs. core memory D flip-flops vs. DRAM Precious space on processor chip vs. off-chip DRAM|3 " xJ -x: " xf -x3J:fl?$Alternatives to Accumulator Machines%P%( If more hardware resources are available, put more fast storage locations alongside the accumulator: Stack machines Register machines Special purpose General purposeZf! "   -f! m@Stack Machines(?Idea: A pile of fast storage locations with a top and a bottom..@ " ? nAStack Machine ISA( Basic operations include: Load: get value from memory and push onto stack Store: pop value off of stack and put into memory Arithmetic: pop 1 or 2 values off of stack; push result on stack Dup: Get value at top of stack without removing; push new copy onto stack (why is this useful?)20222A2`!oB Stack Machine Does A=(B+C)*(D+E)&!( pCStack Machine (cont.)&( qDStack Machines UsedP(Some early computers 8086 floating point unit (sort of& ) Java Virtual Machine (JVM)T " TrERegister MachinesP( Idea: Put more storage locations ( registers ) near the accumulator Regs have names/numbers and can be used instead of memory Accessed much faster than main memory (1-2 CPU cycles vs. ~ 10s to 100 cycles) Far fewer registers than memory locations MIPS has 32 32-bit registers Fewer regs, smaller addresses, fewer bits to name them A scarce resource  use them carefully!E " n` " n) -n* " n| -nE`)*|  ,EUsF&Special- vs. General-Purpose Registers('P&(A special-purpose register is used for specific purposes and there may be limitations on which operations can use it Easier on the HW design: put the reg right where it s needed More difficult for the compiler to use effectively A general-purpose register can be used in any operation - Datapaths more general, hence routing is more difficult u " xp -x8 " x: " xxup89, 1xK'Special-Purpose Registers: The Z-80 CPU((P( Seven 8-bit registers: A, B, C, D, E, H, L (BC, DE, HL can be pairs) Three 16-bit registers: SP, IX, IY, plus PC (Program counter) Add, subtract, shift can only be done to A (8-bit accumulator) Increment and decrement can be done to all regs and reg pairs Can fetch from memory at address (HL) and put in any 8-bit reg A fetch from address (BC) or(DE) can only go to A Fetches from (BC), (HL) and (IX) take different numbers of cycles Anyone want to write a compiler for this?  " > - " + "  ->+>ByL'General Purpose Register (GPR) Machines((P'( The MIPS (and similar processors) has 32 General Purpose Registers (GPRs), each 32 bits long. All can be read or written, except register 0, whichis always 0 and can t be changed. Register access time is uniform. " x,EEF~QGPR Machine Does A=(B+C)*(D+E)(P(fADD $1 M[48], M[76] $R1 = B + C ADD $2 M[20], M[32] $R2 = D + E MUL M[100], $1, $2 $A = R1 * R2g " xge Some Trend From hardware technology: number of Rs can be put on chip has potential grow very fast (Moore s Law ?) Very large register set will have slow access time. Instruction set evolution is slow to accommodate the change of # of Rs,%SMemory and Data Sizes(P(nSo far, we ve only talked about uniform data sizes. Actual data come in many different sizes: Single bits: ( boolean values, true or false) Bytes (8 bits): Characters (ASCII), very small integers Halfwords (16 bits): Characters (Unicode), short integers Words (32 bits): Long integers, floating-point (FP) numbers Double-words (64 bits): Very long integers, double-precision FP Quad-words (128 bits): Quad-precision floating-point numbers^ " Z " ^ $*'-*(,mQ TDifferent Data Sizes(P(How do we handle different data sizes? Pick one size to be the unit stored in a single address Store larger datum in a set of contiguous memory locations Store smaller datum in one location; use shift & mask ops Today, almost all machines (including MIPS) are  byte-addressable  each addressable location in memory holds 8 bits.T' " x " x " (x " xMU MIPS Memory( P (On a byte-addressable machine such as the MIPS, if we say a word (32 bits) is stored  at address 80, we mean it occupies locations 80-83. (The next word would start at 84.) Normally, multi-byte loads and stores must be  aligned. The address of an n-byte load/store must be a multiple of n. For instance, halfwords can only be stored at even addresses. MIPS allow non-aligned loads and stores using special instructions, but they may be slower. (Most processors don t allow this at all!)f " x " ( " x " ( " x3 V2Byte-Order ( Endianness )(P ( For a multi-byte datum, which part goes in which byte? If $1 contains 1,000,000 (F4240H) and we store it into address 80: On a  big-endian machine, the  big end goes into address 80 On a  little-endian machine, it s the other way around8 " xW WBig-Endian vs. Little-Endian(P(, fBig-endian machines: MIPS, Sparc, 68000 Little-endian machines: most Intel processors, Alpha, VAX, Intel 8086 No real reason one is better than the other& Compatibility problems transferring multi-byte data between big-endian and little-endian machines  CAREFUL! [Read Appendix A-43 for more information.]J " , " .XAddressing Modes(P(- An ISA s addressing modes answer the question:  where can operands be located? We have two types of storage in the MIPS (and most other machines): registers and main memory. We can go to either or both for operands. A single operand can come from either a register or a memory location and addressing modes offer various ways of specifying this location.0R "  -gYSimple Addressing Modes(P(IIn these modes, a location or datum is given directly in the instruction:J " JZIndirect Addressing Modes(P(;One or more registers are used to produce a memory address:< " <[Advanced Addressing Modes(P(~Extra features to support features in high-level languages or reduce the number of instructions during common memory accesses: " Z\Choices in Addressing Modes(P(lAnything goes: Any addressing mode may be used for any operand at any time - Easier to map high-level statements directly to instructions - Hard to design processor, due to all the complexity Limited addressing: Only allow a few modes, and/or restrict some operands to certain modes - Harder for compiler/programmer to follow all the rules - Code may be longerFm " x ]Frequency of Addressing Modes(P(>3 programs measured on VAX, which supports all kinds of modes:? " ?^"Empirical Data on Addressing Modes(#P"(How big do the displacements need to be? In study of SPECin92 and SPECfp92, 99% of displacements fell within 215 How big do the immediates (constants) need to be? Studies show: 50% - 60% fit within 8 bits 75%-80% fit within 16 bits ) " J -2 " F -)D# 2  F __!How Do We Represent Instructions?("P!(&We need some bits to tell what operation is performed (e.g., add, sub, mul, etc.)  this is called the opcode. We need some bits for each operand and result (3 total, in our case): What type of addressing mode Number of the register, memory address and/or immediate constanto " x " PF " x^ -xfF^G`Variable-Length Instructions(P(Since the VAX allows any mode for any operand, there could be an instruction with three 32-bit addresses (direct addressing) > 12 bytes in this instruction. But registers need only a few bits to specify, so 12 bytes would be wasteful for an instruction using 3 registers only! Must use variable-length instructions. On the VAX, instructions can vary from 1 to 17 bytes! " x " 2x " x " 2] " x}^aFixed-Length Instructions(P(If every instruction has the same number of bits (preferable a nice even number like 16 or 32), many components of the processor will be simpler. But we either waste some amounts of space or can t support all the addressing modes!B " x " 2U " xdLoading Small IntegersP$All registers in MIPS are 32 bits What if we load a byte or halfword into a reg? Load the bits into the lowest 8 or 16 bits of the reg. Unsigned load: All upper bits set to 0 Signed load: All upper bits set to sign bit (MSB of byte/halfword)d " l "   8><bThe RISC Approach(P(In a Reduced Instruction Set Computer All instructions are the same size (32 bits on the MIPS) Few addressing modes are supported (only the frequent ones) Only a few instruction formats (makes decoding easier!) Arithmetic instructions can only work on registers Data in memory must be loaded into registers before processing - This is called a  load-store architecture^& " x " x- " x&-cRISC Criteria [Colwell 85]. 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Gao  !"#$%&'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ[\]^_`abcdefghijklmnopqrstuvwxyz{|}~      !"#$%&'()*+,-./012345689:;<=>@ABCDEFKRoot EntrydO)PicturesCurrent User?SummaryInformation(d=PowerPoint Document(?DocumentSummaryInformation87Root EntrydO)BdOPicturesCurrent User?SummaryInformation(d=      !"#$%&'()*+,-./0123456@ABCDEFSPQR ՜.+,D՜.+,h$    Letter Paper (8.5x11 in)?/, 2Times New RomanTahoma WingdingsArialSymbol Blueprint'Topic II Instruction-Set Architecture Reading ListThe Stored Memory Computer"Steps in Executing an InstructionWhat is Specified in an ISA?A Simple ISA: Memory-Memory Memory ModelSimple Code TranslationUsing a Temporary Location!Problems with Memory-Memory ISAsAccumulator Machines(Accumulator Machines Does A=(B+C)*(D+E)%Shortcomings of Accumulator Machines;Still, Accumulator Machines Were Common in Early Computers%Alternatives to Accumulator MachinesStack MachinesStack Machine ISA!Stack Machine Does A=(B+C)*(D+E)Stack Machine (cont.)Stack Machines UsedRegister Machines'Special- vs. General-Purpose Registers(Special-Purpose Registers: The Z-80 CPU(General Purpose Register (GPR) MachinesGPR Machine Does A=(B+C)*(D+E) Some TrendMemory and Data SizesDifferent Data Sizes MIPS MemoryByte-Order (Endianness)Big-Endian vs. Little-EndianAddressing ModesSimple Addressing ModesIndirect Addressing ModesAdvanced Addressing ModesChoices in Addressing ModesFrequency of Addressing Modes#Empirical Data on Addressing Modes"How Do We Represent Instructions?Variable-Length InstructionsFixed-Length InstructionsLoading Small IntegersThe RISC ApproachRISC Criteria [Colwell 85]  Fonts UsedDesign Template Slide Titles,4 $, PowerPoint Document(?DocumentSummaryInformation8