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Final Review  a   8"Objectives of CPEG 323`  %Acquire solid knowledge in the analysis, design, implementation and evaluation of computer system organization with emphasis on instruction-set architecture and optimization Acquire basic knowledge of the interaction between system software (e.g. compilers) and hardware (architecture) design $%&b & 9#ABET Outcomes `   Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) Ability to use the techniques, skills and modern engineering tools necessary for engineering practice Knowledge of related topics in computer science disciplinePb  ?)Areas of Importancec(  Basics of computer organization Instruction set architectures Computer arithmetic Computer performance Data path and control Pipelining Memory Hierarchy  " b&   z 2Basics of Computer Organization c$  (Chapter 1 of text + slides Topic0, 1, 1a) General knowledge of computing history Historical perspectives Impacts of technological changes Market forces How architecture is affected by software and applications Basic structure of general purpose computer +? " i -- " +c?cic-c  4Instruction Set Architecturesc(  (Chapter 2 of book + Slides 2, 2a, 2b, 2c. 2d) What is ISA ? Role of ISA w.r.t. hardware and software MIPS instruction set architecture Basic Steps of MIPS instruction executionB/ " /cc  :$ More about ISA & `  ~ 4 style of ISAs: memory-to-memory accumulator machines stack machines register based ISA General vs. special purpose regsFL!`L`!`N    j   ;% More about ISA & `  * MIPS memory model data types and sizes little vs. big endings Register conventions MIPS operations (3 types) instruction format and fields addressing mode assembly vs. machine representation RISC vs. CISC Calling conventions and stack frames caller save vs. callee save parameter passing P.P1PUP3P0PPb.b1bU b 3b0bb4     <& More about ISA & `   System software and ISA role of system software tool chain: compiler, assembler, linker, etc. memory layout for C compilers runtime stack layout Interaction between ISA and OS Privileged mode, traps, etc Static vs. dynamic libraries `5  -`b5bbc a aa  6 Computer Arithmeticc(  (Chapter 3 of book + Topics 3, 3a, 3b, 3c, 3d, 3e) Number representations un/signed integers BCDs Two s complementf3 " ) " 3cc)c&]   ='8Computer Arithmetic  cont d`  Y Basic ALU design Integer adders (ripple carry, look ahead techniques) Integer multiply |F "  " `c(Fc$c(`( X  >(: Computer Arithmetic  cont d`  3 Real numbers IEEE-754 Representation FP Addition44` 3 @1Performance Evaluationa  w(Chapter 2 of book + Slides 4, 4a) Why performance evaluation ? Performance matrices Performance measurement BenchmarksB#U " #cUc x A2Performance matrices  P Time-based matrices CPI MIPS and MFLOPS Hardware based matrics and weakness PQ4 :   B3(Performance measurement and benchmarking))( ) H Sustained and peak performance Relative performance Benchmark classes H C4Processor Datapath and Controlc(&     (Chapter 5 of book + Slides 5, 5a, 5b, 5c) Datapath building blocks Single-cycle datapath and control Multi-cycle datapath and control And comparsion between themB+x " +cxct+          D+Data Path and Control`  E*Data Path and Control`  1-cycle implementation Multi-cycle implementation Finite-state machine Microcode0RG` ` R F, Pipelining `   Chapter 6, slides 6, 6a, 6b, 6c Pipelined data path and control Hazards What are harzards How many types of hazards? Related concept: data dependence and its representation Hazards resolutionLKZeZZK`e``&T  h G-A Pipelined Datapath`&    K5Hazards   Three types of hazards (data, control, structural) Concept of data dependence and dependence graphs Three types of data dependences that cause data hazards   L6 Hazards Detection and Resolution!!( ! w Hazards detection Hazards resolution architecture vs. software methods forwarding (bypassing) stalls and interlock&'Q'Q w M7Memory Hierarchy`  k Chapter 7, slides 7, 7a, 7b, 7c, 7d, 7e Memory hierarchy overview Cache and cache design Virtual memoryll` l H. Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? (Write strategy) bf.bf;bf3bf bfb  N8Cache Architecture  P The basics of cache Cache organization Cache replacement policy Cache design P O9 Cache Basics   What is cache ? Is it architecture visible ? Locality: temporal and spacial Cache hit/miss ratio How to compute effective cache access time ? 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Final Review  a   8"Objectives of CPEG 323`  %Acquire solid knowledge in the analysis, design, implementation and evaluation of computer system organization with emphasis on instruction-set architecture and optimization Acquire basic knowledge of the interaction between system software (e.g. compilers) and hardware (architecture) design $%&b & 9#ABET Outcomes `   Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) Ability to use the techniques, skills and modern engineering tools necessary for engineering practice Knowledge of related topics in computer science disciplinePb  ?)Areas of Importancec(  Basics of computer organization Instruction set architectures Computer arithmetic Computer performance Data path and control Pipelining Memory Hierarchy  " b  2Basics of Computer Organization c$  (Chapter 1 of text + slides Topic0, 1, 1a) General knowledge of computing history Historical perspectives Impacts of technological changes Market forces How architecture is affected by software and applications Basic structure of general purpose computer +? " i -- " +c?cic-c  4Instruction Set Architecturesc(  (Chapter 2 of book + Slides 2, 2a, 2b, 2c. 2d) What is ISA ? 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Final Review  a   8"Objectives of CPEG 323`  %Acquire solid knowledge in the analysis, design, implementation and evaluation of computer system organization with emphasis on instruction-set architecture and optimization Acquire basic knowledge of the interaction between system software (e.g. compilers) and hardware (architecture) design $%&b & 9#ABET Outcomes `   Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) Ability to use the techniques, skills and modern engineering tools necessary for engineering practice Knowledge of related topics in computer science disciplinePb  ?)Areas of Importancec(  Basics of computer organization Instruction set architectures Computer arithmetic Computer performance Data path and control Pipelining Memory Hierarchy  " b  2Basics of Computer Organization c$  (Chapter 1 of text + slides Topic0, 1, 1a) General knowledge of computing history Historical perspectives Impacts of technological changes Market forces How architecture is affected by software and applications Basic structure of general purpose computer +? " i -- " +c?cic-c  4Instruction Set Architecturesc(  (Chapter 2 of book + Slides 2, 2a, 2b, 2c. 2d) What is ISA ? Role of ISA w.r.t. hardware and software MIPS instruction set architecture Basic Steps of MIPS instruction executionB/ " /cc  :$ More about ISA & `  ~ 4 style of ISAs: memory-to-memory accumulator machines stack machines register based ISA General vs. special purpose regsFL!`L`!`N    j   ;% More about ISA & `  * MIPS memory model data types and sizes little vs. big endings Register conventions MIPS operations (3 types) instruction format and fields addressing mode assembly vs. machine representation RISC vs. CISC Calling conventions and stack frames caller save vs. callee save parameter passing P.P1PUP3P0PPb.b1bU b 3b0bb4     <& More about ISA & `   System software and ISA role of system software tool chain: compiler, assembler, linker, etc. memory layout for C compilers runtime stack layout Interaction between ISA and OS Privileged mode, traps, etc Static vs. dynamic libraries `5  -`b5bbc a aa  6 Computer Arithmeticc(  (Chapter 3 of book + Topics 3, 3a, 3b, 3c, 3d, 3e) Number representations un/signed integers BCDs Two s complementf3 " ) " 3cc)c&]   ='8Computer Arithmetic  cont d`  Y Basic ALU design Integer adders (ripple carry, look ahead techniques) Integer multiply |F "  " `c(Fc$c(`( X  >(: Computer Arithmetic  cont d`  3 Real numbers IEEE-754 Representation FP Addition44` 3 @1Performance Evaluationa  w(Chapter 4 of book + Slides 4, 4a) Why performance evaluation ? Performance matrices Performance measurement BenchmarksB#U " #cUc&   n A2Performance matrices  P Time-based matrices CPI MIPS and MFLOPS Hardware based matrics and weakness PQ4 :   B3(Performance measurement and benchmarking))( ) H Sustained and peak performance Relative performance Benchmark classes H C4Processor Datapath and Controlc(&     (Chapter 5 of book + Slides 5, 5a, 5b, 5c) Datapath building blocks Single-cycle datapath and control Multi-cycle datapath and control And comparsion between themB+x " +cxct+          D+Data Path and Control`  E*Data Path and Control`  1-cycle implementation Multi-cycle implementation Finite-state machine Microcode0RG` ` R F, Pipelining `   Chapter 6, slides 6, 6a, 6b, 6c Pipelined data path and control Hazards What are harzards How many types of hazards? Related concept: data dependence and its representation Hazards resolutionLKZeZZK`e``&T  h G-A Pipelined Datapath`&    K5Hazards   Three types of hazards (data, control, structural) Concept of data dependence and dependence graphs Three types of data dependences that cause data hazards   L6 Hazards Detection and Resolution!!( ! w Hazards detection Hazards resolution architecture vs. software methods forwarding (bypassing) stalls and interlock&'Q'Q w M7Memory Hierarchy`  k Chapter 7, slides 7, 7a, 7b, 7c, 7d, 7e Memory hierarchy overview Cache and cache design Virtual memoryll` l H. Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? 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Performance matrices Performance measurement BenchmarksB#U " #cUc x A2Performance matrices  P Time-based matrices CPI MIPS and MFLOPS Hardware based matrics and weakness PQ4 :   B3(Performance measurement and benchmarking))( ) H Sustained and peak performance Relative performance Benchmark classes H C4Processor Datapath and Controlc(&     (Chapter 5 of book + Slides 5, 5a, 5b) Datapath building blocks Single-cycle datapath and control Multi-cycle datapath and control And comparsion between themB'x " 'cxc#            D+Data Path and Control`  E*Data Path and Control`  1-cycle implementation Multi-cycle implementation Finite-state machine Microcode0RG` ` R F, Pipelining `   Chapter 6, slides 6, 6a, 6b, 6c Pipelined data path and control Hazards What are harzards How many types of hazards? Related concept: data dependence and its representation Hazards resolutionLKZeZZK`e``&T  h G-A Pipelined Datapath`&    K5Hazards   Three types of hazards (data, control, structural) Concept of data dependence and dependence graphs Three types of data dependences that cause data hazards   L6 Hazards Detection and Resolution!!( ! w Hazards detection Hazards resolution architecture vs. software methods forwarding (bypassing) stalls and interlock&'Q'Q w M7Memory Hierarchy`  k Chapter 7, slides 7, 7a, 7b, 7c, 7d, 7e Memory hierarchy overview Cache and cache design Virtual memoryll` l H. Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? (Write strategy) bf.bf;bf3bf bfb  N8Cache Architecture  P The basics of cache Cache organization Cache replacement policy Cache design P O9 Cache Basics   What is cache ? Is it architecture visible ? Locality: temporal and spacial Cache hit/miss ratio How to compute effective cache access time ? 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Final Review  a   8"Objectives of CPEG 323`  %Acquire solid knowledge in the analysis, design, implementation and evaluation of computer system organization with emphasis on instruction-set architecture and optimization Acquire basic knowledge of the interaction between system software (e.g. compilers) and hardware (architecture) design $%&b & 9#ABET Outcomes `   Ability to apply knowledge of science (e.g., computer architecture and system organization, and related computer science issues), and engineering (e.g., performance analysis and benchmarking, ISA simulation and verification) Ability to use the techniques, skills and modern engineering tools necessary for engineering practice Knowledge of related topics in computer science disciplinePb  ?)Areas of Importancec(  Basics of computer organization Instruction set architectures Computer arithmetic Computer performance Data path and control Pipelining Memory Hierarchy  " b  2Basics of Computer Organization c$  (Chapter 1 of text + slides Topic0, 1, 1a) General knowledge of computing history Historical perspectives Impacts of technological changes Market forces How architecture is affected by software and applications Basic structure of general purpose computer +? " i -- " +c?cic-c  4Instruction Set Architecturesc(  (Chapter 2 of book + Slides 2, 2a, 2b, 2c. 2d) What is ISA ? Role of ISA w.r.t. hardware and software MIPS instruction set architecture Basic Steps of MIPS instruction executionB/ " /cc  :$ More about ISA & `  ~ 4 style of ISAs: memory-to-memory accumulator machines stack machines register based ISA General vs. special purpose regsFL!`L`!`N    j   ;% More about ISA & `  * MIPS memory model data types and sizes little vs. big endings Register conventions MIPS operations (3 types) instruction format and fields addressing mode assembly vs. machine representation RISC vs. CISC Calling conventions and stack frames caller save vs. callee save parameter passing P.P1PUP3P0PPb.b1bU b 3b0bb4     <& More about ISA & `   System software and ISA role of system software tool chain: compiler, assembler, linker, etc. memory layout for C compilers runtime stack layout Interaction between ISA and OS Privileged mode, traps, etc Static vs. dynamic libraries `5  -`b5bbc a aa  6 Computer Arithmeticc(  (Chapter 3 of book + Topics 3, 3a, 3b, 3c, 3d, 3e) Number representations un/signed integers BCDs Two s complementf3 " ) " 3cc)c&]   ='8Computer Arithmetic  cont d`  Y Basic ALU design Integer adders (ripple carry, look ahead techniques) Integer multiply |F "  " `c(Fc$c(`( X  >(: Computer Arithmetic  cont d`  3 Real numbers IEEE-754 Representation FP Addition44` 3 @1Performance Evaluationa  w(Chapter 4 of book + Slides 4, 4a) Why performance evaluation ? Performance matrices Performance measurement BenchmarksB#U " #cUc x A2Performance matrices  P Time-based matrices CPI MIPS and MFLOPS Hardware based matrics and weakness PQ4 :   B3(Performance measurement and benchmarking))( ) H Sustained and peak performance Relative performance Benchmark classes H C4Processor Datapath and Controlc(&     (Chapter 5 of book + Slides 5, 5a, 5b) Datapath building blocks Single-cycle datapath and control Multi-cycle datapath and control And comparsion between themB'x " 'cxc#            D+Data Path and Control`  E*Data Path and Control`  1-cycle implementation Multi-cycle implementation Finite-state machine Microcode0RG` ` R F, Pipelining `   Chapter 6, slides 6, 6a, 6b, 6c Pipelined data path and control Hazards What are harzards How many types of hazards? Related concept: data dependence and its representation Hazards resolutionLKZeZZK`e``&T  h G-A Pipelined Datapath`&    K5Hazards   Three types of hazards (data, control, structural) Concept of data dependence and dependence graphs Three types of data dependences that cause data hazards   L6 Hazards Detection and Resolution!!( ! w Hazards detection Hazards resolution architecture vs. software methods forwarding (bypassing) stalls and interlock&'Q'Q w M7Memory Hierarchy`  k Chapter 7, slides 7, 7a, 7b, 7c, 7d, 7e Memory hierarchy overview Cache and cache design Virtual memoryll` l H. Q1: Where can a block be placed in the upper level? (Block placement) Q2: How is a block found if it is in the upper level? (Block identification) Q3: Which block should be replaced on a miss? (Block replacement) Q4: What happens on a write? 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MillsDavid L. Millsuter performance Data path and control Pipelining Memory Hierarchy  " b  2Basics of Computer Organization c$  (Chapter 1 of text + slides Topic0, 1, 1a) General knowledge of computing history Historical perspectives Impacts of technological changes Market forces How architecture is affected by software and applications Basic structure of general purpose computer +? " i -- " +c?cic-c  4Instruction Set Architecturesc(  (Chapter 2 of book + Slides 2, 2a, 2b, 2c. 2d) What is ISA ? Role of ISA w.r.t. hardware and software MIPS instruction set architecture Basic Steps of MIPS instruction executionB/ " /cc  :$ More about ISA & `  ~ 4 style of ISAs: memory-to-memory accumulator machines stack machines register based ISA General vs. special purpose regsFL!`L`!`N    j   ;% More about ISA & `  * MIPS memory model data types and sizes little vs. big endings Register conventions MIPS operations (3 types) instruction format and fields addressing mode assembly vs. machine representation RISC vs. CISC Calling conventions and stack frames caller save vs. callee save parameter passing P.P1PUP3P0PPb.b1bU b 3b0bb4     <& More about ISA & `   System software and ISA role of system software tool chain: compiler, assembler, linker, etc. memory layout for C compilers runtime stack layout Interaction between ISA and OS Privileged mode, traps, etc Static vs. dynamic libraries `5  -`b5bbc a aa  6 Computer Arithmeticc(  (Chapter 3 of book + Topics 3, 3a, 3b, 3c, 3d, 3e) Number representations un/signed integers BCDs Two s complementf3 " ) " 3cc)c&]   ='8Computer Arithmetic  cont d`  Y Basic ALU design Integer adders (ripple carry, look ahead techniques) Integer multiply |F "  " `c(Fc$c(`( X  >(: Computer Arithmetic  cont d`  3 Real numbers IEEE-754 Representation FP Addition44` 3 @1Performance Evaluationa  w(Chapter 4 of book + Slides 4, 4a) Why performance evaluation ? Performance matrices Performance measurement BenchmarksB#U " #cUc x A2Performance matrices`  P Time-based matrices CPI MIPS and MFLOPS Hardware based matrics and weakness "PQ`4 :   B3(Performance measurement and benchmarking))b( ) H Sustained and peak performance Relative performance Benchmark classesII` H C4Processor Datapath and Controlc(&     (Chapter 5 of book + Slides 5, 5a, 5b) Datapath building blocks Single-cycle datapath and control Multi-cycle datapath and control And comparsion between themB'x " 'cxct'          D+Data Path and Control`  E*Data Path and Control`  1-cycle implementation Multi-cycle implementation Finite-state machine Microcode0RG` ` R F, Pipelining `   Chapter 6, slides 6, 6a, 6b, 6c Pipelined data path and control Hazards What are hazards How many types of hazards? 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