ELEG 867 Nanotechnology
Homework #2 - due Thursday, 20 September 2001, before 4:30 pm

1. Feynmann’s talk (see Hwk 1) described storing bits 3-dimensionally using cubes of 5x5x5= 125 atoms. Assume that we built such a structure by MBE or MOCVD, followed by ebeam lithography (or x-ray lithography). For convenience, assume that the 125 atom dots are Ge, and that the substrate and the matrix surrounding the dots are Si. Assume that along the x direction, 5 atoms of Si (lattice constant a= 0.5431 nm) separate the 5 atoms of Ge (a= 0.5658 nm). Along one cubic axis, the resulting structure will then be: (SiSiSiSiSi)(GeGeGeGeGe)(SiSiSiSiSi)(Ge… etc.. Neglect any lattice strain effects and assume that in each region the atoms take on their bulk lattice constant with no dislocations. What is the bit density on the surface (per cm^-2) i.e. of one layer? What is the volume density of bits for multiple layers? What area is needed to store one Terabit on one surface layer? For a 1 cm² area, how many bits are stored in 10 layers?

2. In the above problem, assume that the electron density differs in the Si versus the Ge dot regions such that x-rays will diffract from the periodic 3D array, similarly to x-ray diffraction from a conventional crystal. Assume that each dot bit is “on”, or equal in its diffractive effects (i.e. a 1111… pattern for all bits on). Use Bragg’s Law of diffraction to calculate a convenient x-ray wavelength that will yield a first order diffraction peak at an angle of 45 degrees. Now assume that every other bit is off (i.e. the pattern is 101010… along any axis) - what will the new diffraction angle be? A typical lab x-ray diffractometer uses an x-ray tube producing Cu Ka radiation with l = 0.154 nm. What is the first order diffraction angle with this wavelength for the 1111 bit case? Discuss the feasibility of x-rays for “reading” the bit pattern of quantum dot arrays.

3. Consider the following excerpt from the press release given on the web page:

http://www.spectrum.ieee.org/WEBONLY/resource/sep01/ntran.html

“Intel’s latest transistor, built by researchers at the company’s new Components Research Laboratory in Hillsboro, Ore., and unveiled 10 June at the 2001 Silicon Nanoelectronics Workshop in Kyoto, Japan, has the narrowest gate ever built: only 20 nm across, or 30 percent thinner than Intel’s previous record. What’s more, the gate oxide layer separating the polysilicon gate electrode from the transistor’s silicon base is only 0.8 nm thick, or less than three atomic layers deep. To get the size reductions, researchers used a proprietary lab technique adapted from current 248-nm phase-shift mask lithography, in which interference between light waves serves to create patterns much smaller than the wavelength of the light itself. Shrinking the gate and the gate oxide vastly improved the speed of the new transistor; it can switch on and off at a blinding 1.5 terahertz, 25 percent faster than the previous benchmark.”

Using the parameters given above, perform the following analysis of this transistor: Use the equation for cutoff frequency f_T = v_sat/2pL_g to estimate the carrier saturation velocity at 1.5 terahertz. Is this value realistic? Calculate the gate capacitance per area (fF per square micron). Assuming that the width of the gate region is 5 times the gate length (5 = W/L), how many electrons are stored (total number) on the gate capacitor with an applied gate voltage of 1 volt above threshold.

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