1. Design the gate insulator for an nMOS transistor in the technology node of 90 nm, which is currently under development.  Assume that the gate length is 90 nm, and that the width to length ratio, W/L = 3. Choose a binary oxide from Table 3 on page 370 of Waser, with known dielectric constant k, energy gap and band offsets.  You may use a different insulator if you have all the data needed.  Assume that you fabricate the gate insulator with actual thickness, d_insul = 2 nm.  Questions:
(a) calculate the effective oxide thickness, EOT.
(b) what is the actual capacitance per area? - put your answer in units of femtoFarads per square micron.
(c) if the electric field strength for dielectric breakdown is 10 MV/cm, calculate the breakdown voltage of your gate.
(d) draw your MOS band diagram under flat band conditions, labeling the band offsets (hint use Fig. 17, p. 372), using your choice of metal, (e.g. Al), and p-type Si.
(e)  if there are no defect charges (don't you wish), calculate the flat band voltage, using the work function of p-type silicon as given on p. 362 of Waser.
(f) if there is a parasitic layer of SiO₂ with thickness 0.2 nm, what is the actual capacitance of the net insulator?
 

2. Name your favorite MIS gate insulator material for high performance FETs, and give 3 reasons to support your claim.  (your score will depend on the thoroughness of your answer).
 
 
 

  Homework assignments will appear on the web at: http://www.ece.udel.edu/~kolodzey/courses/eleg667_016f04.html
  Note: On each homework and report submission, you must please give your name, the due date, assignment number and the course number.