Homework #11 - due Thursday, 18 May 2006, 4 pm in Dept. Office (140 Evans Hall)

1.  Problem 8.8 in chapter 8 of Muller & Kamins, p.423 in 3rd edition (Hint: this is a p- channel device - pMOS).

2.  Problem 8.9 in chapter 8 of Muller & Kamins, p.423 in 3rd edition (Note typo- error: use Table 8.2 on p. 390, not Table 8.1).

3.  Problem 8.12, (a) only in chapter 8 of Muller & Kamins, p.423 in 3rd edition.

4.  Problem 8.14 in chapter 8 of Muller & Kamins, p.423 in 3rd edition. Show plots for (i) and (ii) for p-type substrate only - not the n- substrate that is shown in Fig. P.14.
 

5.  Problem 8.19 in chapter 8 of Muller & Kamins, p.425 in 3rd edition (Hint: the voltage ramp, Rm, is fast enough that CdV/dt is significant through the gate oxide).
 

  Homework assignments will appear on the web at: http://www.ece.udel.edu/~kolodzey/courses/eleg646s06.html
  Note: On each homework and report submission, please give your name, the due date, assignment number and the course number. For full credit - include units/dimensions for all numerical quantities