1. Calculate the high level noise margin, NMH, for a CMOS inverter with kn/kp = 2.5. This will more nearly reflect our class circuits.
Briefly discuss a comparison of your NMH value with the NML that we calculated in class for the special case: kn/kp = 1.

2. Submit a first draft L-Edit plot of your CMOS logic circuit project.
Please plot a composite with all 5 layers on one page with easy-to-read fill patterns
Indicate overlaps and use lambda = 6 microns. Indicate distances and include a legend of layer fill patterns.
For full credit, on a separate page, include the circuit schematic, logic gate diagram, Boolean expression and the truth table.
Hint: this assignment will be graded on general features, not layout efficiency. Do not worry (yet) about optimizing the layout.

See Graphics Layout Editors Site website for printing hints.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
the due date, assignment number and the course.