1. Submit an L-Edit plot of a CMOS inverter. Show and label input, output, VDD and ground. Use the old EE650 design rules for L, Z and overlaps - i.e lambda = 6 microns. Indicate distances and include a legend of layer fill patterns.

2. Submit a transistor circuit diagram (transistor symbols, not a layout plot) of your CMOS circuit project. Your project circuit may use NANDs, NORs and Inverters. For ease of fabrication, however, keep the total number of transistors to below about 20, and use 3 or less input and output lines, plus 2 more for VDD and ground. Feel free to depart from your previous submission.
Re-include the Boolean expression and Truth table (else it will be too difficult to grade). Hint: now is the time for any modifications to your previous design.

See Graphics Layout Editors Site website for printing hints.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
the due date, assignment number and the course.