ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #5 - due Wednesday, 14 March 2001

1. Calculate the threshold voltage of an nMOS transistor with an Al metal gate, gate oxide thickness of 20 nm, and p-type substrate acceptor doping concentration of 1 E 17 cm^-3. Let the net oxide trapped charge be Qox/q = 1 E 10 cm^-2. This device will be similar to our EE 650 transistor.

2. Submit a logic diagram of a simple circuit (e.g. NAND/NOR) with truth table and logic symbols.
(no transistor diagram is needed in this assignment). Give 1 or 2 sentences why you chose this circuit.

See Graphics Layout Editors Site website for printing hints.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/

Note: On each homework and report submission, give your name,
the due date, assignment number and the course.