HIPS 2014

19th International Workshop on High-Level Parallel Programming Models and Supportive Environments

Held in Conjunction With


The 19th HIPS workshop, to be held as a full-day meeting on May 19, 2014 at the IPDPS 2014 conference in Phoenix, focuses on high-level programming of multiprocessors, compute clusters, and massively parallel machines. Like previous workshops in the series, which was established in 1996, this event serves as a forum for research in the areas of parallel applications, language design, compilers, runtime systems, and programming tools. It provides a timely and lightweight forum for scientists and engineers to present the latest ideas and findings in these rapidly changing fields. In our call for papers, we especially encouraged innovative approaches in the areas of emerging programming models for large-scale parallel systems and many-core architectures.

Topics of Interest

Topics of interest to the HIPS workshop include but are not limited to:


Time Event
8:15 -- 8:30 Opening Remarks
8:30 -- 9:30 Title: The (Parallel) BGL: A High-Performance Parallel Graph Algorithms Library
Andrew Lumsdaine
Professor, Computer Science Department, Indiana University
Director, Center for Research in Extreme Scale Technologies (CREST)

Abstract: Graphs and graph algorithms have long been a fundamental abstraction in computer science and many types of data-driven applications - the emerging "fourth pillar" of science - depend on graph computations. The resource requirements for graph computations can be quite large, however, running graph algorithms on today's HPC systems presents a number of challenges - the paradigms, software, and hardware that have worked well for mainstream scientific applications are not well matched to large-scale graph problems.
In this talk we present the design and implementation of multiple generations of the Boost Graph Library, a library of reusable high-performance software components for graph computation. The original (sequential) BGL applies the paradigm of generic programming to the domain of graph computations. Subsequent (parallel) generations of the BGL were able to be built from the sequntial BGL lifting away the implicit requirements of sequential execution and a single shared address space. This process allows us to create generic algorithms having sequential expression and requiring only the introduction of parallel data structures for parallel execution. By characterizing these extensions as well as the extension process, we develop general principles and patterns for using (and reusing) generic parallel software libraries. We demonstrate that the resulting algorithm implementations are both efficient and scalable with performance results for several algorithms implemented in the open-source Parallel Boost Graph Library. We conclude by discussing on-going and future work, most notably the new active-message system being incorporated into PBGL to enable efficient execution on multi-core, hybrid, and exascale architectures.
9:30 -- 10:00 Coffee Break

Session 1: System Support

10:00 -- 10:30 Bohrium: A Virtual Machine Approach to Portable Parallelism
Mads R. B. Kristensen, Simon Andreas Frimann Lund, Troels Blum, Kenneth Skovhede, Brian Vinter
10:30 -- 11:00 HATI: Hardware Assisted Thread Isolation for Concurrent C/C++ Programs
Juan Carlos Martinez Santos
11:00 -- 11:30 A General Model Checking Framework for Various Memory Consistency Models
Tatsuya Abe, Toshiyuki Maeda
11:30 -- 1:30 Lunch

Session 2: Optimization

1:30 -- 2:00 Autotuning Tensor Transposition
Lai Wei, John Mellor-Crummey
2:00 -- 2:30 Automatic MPI-IO Tuning with the Periscope Tuning Framework
Weifeng Liu, Isaias A. Compres Urena, Michael Gerndt, Bin Gong
2:30 -- 3:00 Optimizing Collective Communication in UPC
Jithin Jose, Khaled Hamidouche, Jie Zhang, Akshay Venkatesh, Dhabaleswar Panda
3:00 -- 3:30 Coffee Break

Session 3: Effective Communication

3:30 -- 4:00 SWIFT: A Transparent and Flexible Communication Layer for PCIe-coupled Accelerators and (Co-)Processors
Stefan Lankes, Simon Pickartz, Pablo Reble, Carsten Clauss
4:00 -- 4:30 Deterministic Synchronization of Multi-Threaded Programs with Spawn and Merge
Christopher Boelmann, Lorenz Schwittmann, Torben Weis
4:30 -- 5:00 ABC2: Adaptively Balancing Computation & Communication in a DSM cluster of Multicores for Irregular Applications
Sai Charan Koduru, Keval Vora, Rajiv Gupta

Submission & Deadlines

EXTENDED :: New Submission due date: January 24, 2014

Author notification: March 14, 2014

Camera-ready papers: March 31, 2014

Paper Submission

Submit papers for the workshop using the EasyChair conference system. Submission for Paper.

Paper Style

The HIPS paper style is identical to the IPDPS paper style. Submitted manuscripts may not exceed 10 single-spaced double-column pages using 10-point size font on 8.5x11 inch pages (IEEE conference style), including figures, tables, and references.

Paper Templates


Workshop Chair

Steering Committee

Program Committee


Conference Date Location
18th HIPS 2013 May 20, 2013 Boston, MA, USA
17th HIPS 2012 May 21, 2012 Shanghai, China
16th HIPS 2011 May 20, 2011 Anchorage, Alaska, USA
15th HIPS 2010 April 19-23, 2010 Atlanta, GA, USA
14th HIPS 2009 May 25, 2009 Rome, Italy
13th HIPS 2008 April 14, 2008 Miami, FL, USA
12th HIPS 2007 March 26, 2007 Long Beach, California, USA
11th HIPS 2006 April 25, 2006 Rhodes Island, Greece
10th HIPS 2005 April 4, 2005 Denver, Colorado, USA
9th HIPS 2004 April 26, 2004 Santa Fe, New Mexico, USA
8th HIPS 2003 April 22, 2003 Nice, France
7th HIPS 2002 April 15, 2002 Fort Lauderdale, FL, USA
6th HIPS 2001 April 23, 2001 San Francisco, CA, USA
5th HIPS 2000 May 1, 2000 Cancun, Mexico
4th HIPS 1999 April 12, 1999 San Juan, Puerto Rico, USA
3rd HIPS 1998 March 30, 1998 Orlando, FL, USA
2nd HIPS 1997 April 1, 1997 Geneva, Switzerland
1st HIPS 1996 April 16, 1996 Honolulu, HI, USA