.TITLE "Precision Radio Clock for Station WWV/H Transmissions" ; ; See readme.txt file in this distribution for copyright notice, setup ; instructions and command summary. ; ; Include files ; .NOLIST #INCLUDE "regs.inc" ; TMS320 registers #INCLUDE "ports.inc" ; DSP93 ports #INCLUDE "serial.inc" ; 16550 UART .LIST ; ; Program memory map ; ; External 1000-7fff program ; ; Data memory map ; ; Block B2 0060-007f interrupt variables and stack ; Block B0 0200-02ff filter coefficients (mapped to prog mem) ; Block B1 0300-03ff filter delay lines ; External 0400-7fff program variables ; ; Auxiliary register usage ; ; AR0 utility compare and temporary register ; AR1 utility pointer ; AR2 utility counter/pointer ; AR3 reserved for interrupt routines ; AR4 reserved for interrupt routines ; AR5 interrupt stack pointer ; AR6 AIO buffer pointer ; AR7 AIO buffer pointer ; ; General purpose status bits (STATUS) ; SSYNC .EQU 0 ; second sync MSYNC .EQU 1 ; minute sync DGATE .EQU 2 ; data gate BGATE .EQU 3 ; data bit error INSYNC .EQU 4 ; clock is synchronized LEPSEC .EQU 5 ; leap second in progress WWVH .EQU 6 ; WWV (0) WWVH (1) select ERRSTA .EQU 8 ; error condition (buffer overrun) LEAPYR .EQU 9 ; leap year flag DGSYNC .EQU 10 ; digit compare error POPOFF .EQU 11 ; frequency popoff ; ; Miscellaneous status bits (MISC) ; ; These bits correspond to designated bits in the IRIG timecode. The bit ; probabilities are exponentially averaged over several minutes and ; processed by a integrator and decision circuit. ; DUT1 .EQU 0 ; 56 DUT .1 DUT2 .EQU 1 ; 57 DUT .2 DUT4 .EQU 2 ; 58 DUT .4 DUTS .EQU 3 ; 50 DUT sign DST1 .EQU 4 ; 55 DST1 DST in progress DST2 .EQU 5 ; 2 DST2 DST change warning SECWAR .EQU 6 ; 3 leap second warning ; ; Alarm status bits (ALARM) ; ; These bits indicate various alarm conditions, which are decoded to ; form the quality character included in the timecode. There are four ; four-bit nibble fields in the word, each corresponding to a specific ; alarm condition. At the end of each minute, the word is shifted left ; one position and the two least significant bits of each nibble ; cleared. The least significant two bits are set if the associated ; alarm condition is raised during the minute. The least significant bit ; is cleared at the end of each second. The least significant bit of ; some nibbles is indicated by a panel LED; the most significant bits ; are decoded for the quality character. ; DECERR .EQU 0 ; BCD digit decoding error SYMERR .EQU 4 ; low symbol probability MODERR .EQU 8 ; too many data bit errors SYNERR .EQU 12 ; low 1-s or 1-m sync pulse amplitude ; ; AIO Configuration constants: HPF out, sync, 3-V half scale, sin x/x. ; RA is chosen to get the SCF as close to 288 kHz as possible; RB is ; chosen to get the sample frequency as close to 8000 Hz as possible. ; This results in a nominal A/D sample frequency of 7949 Hz and 3-dB ; bandwidth of about 10-3700 Hz at the A/D input. ; CFGA .EQU CMDA_VAL(17) ; AIO load RA=TA=17 for SCF 294.1 kHz CFGB .EQU CMDB_VAL(37) ; AIO load RB=TB=37 for 7949 Hz AIO_GAIN .EQU AIO_GAIND60|AIO_GAIND70 ; AIO gain CFGC .EQU AIO_CONFIG|AIO_SYNC|AIO_GAIN|AIO_INSSINX ; ; Tone frequency definitions. Note the nominal sample frequency of 7949 ; Hz must be corrected to 8000 Hz by replicating samples at intervals of ; about 157 samples, which is equivalent to adding about 420 to the low ; order word of the epoch counter for each sample. ; COMSIZ .EQU 8000 ; Sample clock frequency (Hz) INCR2 .EQU 420 ; LSW 420.47248 sample clock adjust MS .EQU 8 ; actual samples per millisecond IN1000 .EQU 10 ; 1000 Hz increment, 4.5-deg sin table IN1200 .EQU 12 ; 1200 Hz increment, 4.5-deg sin table ; ; Sizes of arrays ; OUTSIZ .EQU 1000 ; size of character circular buffers BUFSIZ .EQU 50 ; size of AIO buffer (6.25 ms) MEDSIZ .EQU 5 ; size of sync median filter (5 ms) IGRSIZ .EQU 170*MS ; size of data matched filter DATSIZ .EQU 60 ; size of index/data second buffers BCDSIZ .EQU 4*10 ; size of BCD coefficient table ; ; Odds and ends ; P1_MSK .EQU PTT_R1+FREQ_UP_R1+FREQ_DN_R1 ; RADIO_CTRL port 1 mask FIRLEN .EQU 41 ; number of FIR coefficients P15 .EQU 32767 ; max positive number M15 .EQU -P15 ; max negative number LIMIT .EQU 10000 ; limiter threshold (LED 1) MAXAVG .EQU 8-1 ; max time constant (8 = 256 s) AVGINC .EQU 4000h ; LSW averaging interval increment PDELAY .EQU 188 ; default propagation delay (23.5 ms) TCONST .EQU 4-1 ; log2 time constant (about 16 minutes) ; ; Thresholds. These establish the minimum signal level, minimum SNR and ; maximum jitter thresholds which establish the error and false alarm ; rates of the receiver. The values defined here may be on the ; adventurous side in the interest of the highest sensitivity. ; CTHR .EQU 10 ; 1-s synch compare threshold STHR .EQU 1500 ; 1-s sync threshold MTHR .EQU 500 ; 1-m sync threshold DTHR .EQU 1000 ; data amplitude threshold NTHR .EQU 100 ; data SNR threshold (dB * 10) ETHR .EQU 1000 ; digit correlator threshold TTHR .EQU 30 ; digit SNR threshold (dB * 10) BTHR .EQU 30 ; max bit error count in second ; ; Nonprinting and special character codes ; LF .EQU 0Ah ; ASCII line feed CR .EQU 0Dh ; ASCII carriage return ; ; Interesting block addresses and memory page pointers ; B_PAGE .EQU 0h ; base page pointer U_PAGE .EQU 8h ; user page pointer U_ADDR .EQU U_PAGE<<7 ; user page address B0P .EQU 0FF00h ; block B0 program address B0D .EQU 0200h ; block B0 data address B1D .EQU 0300h ; block B1 data address ; ; Following are variables accessed by either absolute or indirect ; addressing modes. ; ; Program variables in internal memory (block B0) initialized by ; program. Addresses ending in P are valid following a CNFP ; instructuion, which maps block B0 to program memory. Other addresses ; are valid following a CNFD instruction, which maps block B0 to data ; memory. ; BCDDLD .EQU B0D ; matched filter coefficients BCDDLP .EQU BCDDLD+B0P-B0D ; ibid in program memory DELBPF .EQU BCDDLD+BCDSIZ ; bandpass filter delay line DELLPF .EQU DELBPF+FIRLEN+1 ; lowpass filter delay line DELMF .EQU DELLPF+FIRLEN+1 ; matched filter delay line B0DEND .EQU DELMF+FIRLEN+1 ; end of block B0 ; ; Program variables in internal memory (block B1) cleared at reset. ; ; The decoding matrix consists of nine row vectors, one for each digit ; of the timecode. Each vector includes (1) the current clock digit, (2) ; an 11-stage shift register used to save the current probabilities for ; each of the ten possible digit values plus a carry value, (3) the most ; recent maximum-likelihood digit decoded and (4) a compare counter. The ; digits are stored from least to most significant order. The timecode ; is formed from the digits of maximum value reading in the opposite ; order: yy ddd hh:mm. ; ; Decoding vector format ; DECVEC .EQU 0 ; current clock digit DECTMP .EQU DECVEC+1 ; temporary for shift DECINT .EQU DECTMP+1 ; digit integrator 0-9 DECLST .EQU DECINT+10 ; (2) last digit decode and count DECSIZ .EQU DECLST+2 ; end of vector ; MNPROB .EQU B1D ; minutes (2 digits) HRPROB .EQU MNPROB+(2*DECSIZ) ; hours (2 digits) DAPROB .EQU HRPROB+(2*DECSIZ) ; days (3 digits) YRPROB .EQU DAPROB+(3*DECSIZ) ; years (2 digits) EDPROB .EQU YRPROB+(2*DECSIZ) ; end of decoding table STACK .EQU B1D+100h ; interrupt stack (grows down) B1DEND .EQU STACK ; end of block B1 ; ; Program variables in external memory (U_PAGE) cleared at reset. We ; protect one location at the beginning for I/O status. ; USRBGN .EQU U_ADDR+1 ; beginning of clear region ; ; The AIO buffer is a circular structure indexed by AR6 and AR7. AR6 is ; used only by interrupt routines. The receive interrupt routine stores ; the sample at AR6 and then increments AR6. The transmit interrupt ; routine loads the sample at AR6, which is the oldest in the circular ; buffer. The main program loops until AR7 is not equal to AR6, then ; loads the sample found at AR7, which is the oldest sample not yet ; processed. The program loads the output at AR7 and then increments ; AR7. Since input and output interrupts are synchronous, no data are ; lost or duplicated. ; INTBUF .EQU U_ADDR+100h ; AIO buffer ; ; Circular buffers and buffer structures are used for character I/O, one ; set each for input (modem and echo to UART) and output (UART to ; modem). ; ; Buffer structure format ; 0 address of first word beyond buffer ; 1 address of first word of buffer ; 2 put pointer ; 4 get pointer ; INPBCB .EQU INTBUF+BUFSIZ ; input buffer structure OUTBCB .EQU INPBCB+4 ; output buffer structure INPBUF .EQU OUTBCB+4 ; input circular buffer OUTBUF .EQU INPBUF+OUTSIZ ; output circular buffer ; ; Filter structures ; COMB .EQU OUTBUF+OUTSIZ ; 1000/1200-Hz comb filter IGRTAB .EQU COMB+COMSIZ ; matched filter for timecode modulation PPITAB .EQU IGRTAB+(IGRSIZ*2) ; minute buffer for 1-m sync SECTAB .EQU PPITAB+(DATSIZ*2) ; minute buffer for data values BCDCOD .EQU SECTAB+DATSIZ ; matched filter coefficients USREND .EQU BCDCOD+BCDSIZ ; end of clear region ; ; Following are variables accessed by direct addressing mode. These are ; offsets relative the the data page pointer. ; : Program variable offsets in block B2 (B_PAGE) initialized at startup. ; TNC_BUF .EQU 60h ; TNC_OUTPUT port status PDC_BUF .EQU 61h ; RADIO_CTRL port status ; ; Program variable offsets in block B2 (B_PAGE) uninitialized. ; UARTI .EQU 62h ; UART input buffer UARTO .EQU 63h ; UART output buffer UARTC .EQU 64h ; UART modem control buffer UARTL .EQU 65h ; UART divisor latch XTMP .EQU 66h ; temp ; ; Program variable offsets in external memory (U_PAGE) initialized at ; startup. ; PIO_BUF .EQU 00h ; RADIO_GAIN port status ; ; Program variable offsets in external memory (U_PAGE) cleared at reset. ; ; Analog signal variables ; INPSIG .EQU 01h ; AIO input buffer F400 .EQU 02h ; 400-Hz bandpass filter F150 .EQU 03h ; 150-Hz lowpass filter SYNC .EQU 04h ; 1-s sync signal IRIG .EQU 05h ; (2) 100-Hz I phase integrator QRIG .EQU 07h ; (2) 100-Hz Q phase integrator IGRPTR .EQU 09h ; 100-Hz integrator pointer IGRATE .EQU 0Ah ; (2) 1000/1200-Hz I phase integrator QGRATE .EQU 0Ch ; (2) 1000/1200-Hz Q phase integrator PPIPTR .EQU 0Eh ; 1000/1200-Hz integrator pointer ; ; Variables used to establish 1-s sync epoch within the second and ; discipline master oscillator frequency ; SYNPTR .EQU 10h ; 1-s sync integrator pointer MAX .EQU 11h ; 1-s sync max amplitude TEPOCH .EQU 12h ; 1-s sync epoch at max amplitude TREG .EQU 13h ; (3) 1-s sync epoch median filter XEPOCH .EQU 16h ; 1-s sync epoch (for compare) YEPOCH .EQU 17h ; 1-s sync epoch ZEPOCH .EQU 18h ; 1-s sync saved last interval SYNCNT .EQU 19h ; 1-s sync run-length counter JITCNT .EQU 1Ah ; 1-s sync run-length counter AVGCNT .EQU 1Bh ; averaging interval counter AVGINT .EQU 1Ch ; (2) log2 averaging time PPIMAX .EQU 1Eh ; 1-m sync max amplitude PPIPOS .EQU 1Fh ; 1-m sync epoch at max amplitude ; ; Variables used to establish basic system timing ; EPOCH .EQU 20h ; epoch ramp FUDGE .EQU 21h ; (2) epoch phase INCRX .EQU 23h ; (2) epoch frequency MILLI .EQU 25h ; 1000/1200-Hz ramp CYCLE .EQU 26h ; (2) 100-Hz ramp RPHASE .EQU 28h ; 1-s ramp at receiver RSEC .EQU 29h ; receiver seconds counter ; ; Variables used to establish the second, minute and day ; CDELAY .EQU 30h ; WWV propagation delay HDELAY .EQU 31h ; WWVH propagation delay TPHASE .EQU 32h ; 1-s ramp at transmitter TSEC .EQU 33h ; second of minute (0-59/60) MINUTE .EQU 34h ; minute of day (0-1439) DAY .EQU 35h ; day of year (1-365/366) MINSET .EQU 36h ; minutes since last set ONE .EQU 37h ; the one and only one ; ; Variables used for data bit decoding and threshold correction ; DPULSE .EQU 40h ; data bit pulse length P0 .EQU 41h ; P(0) probability P1 .EQU 42h ; P(1) probability P2 .EQU 43h ; P(2) probability BIT .EQU 44h ; most recent bit value (P1-P0) ; ; Variables used to estimate signal levels and bit/digit probabilities ; SECAMP .EQU 45h ; 1-s sync amplitude (for debug) MINAMP .EQU 46h ; 1-m sync amplitude DATAMP .EQU 47h ; max signal amplitude NOIAMP .EQU 48h ; average noise amplitude DATSNR .EQU 49h ; data SNR (dB * 10) DIGAMP .EQU 4Ah ; max digit amplitude DIGSNR .EQU 4Bh ; digit SNR (dB * 10) ; ; Variables used to establish status and alarm conditions ; STATUS .EQU 50h ; status bits MISC .EQU 51h ; miscellaneous timecode bits ALARM .EQU 52h ; alarm flashers ERRCNT .EQU 53h ; data bit error counter ; ; Signal generators for AIO output ; AIOPTR .EQU 55h ; AIO output pointer SECRMP .EQU 56h ; 1-m ramp (AIO only) HZ1000 .EQU 57h ; 1000/1200-Hz sinewave (AIO only) HZ100 .EQU 58h ; 100-Hz sinewave (AIO only) ; ; Command interpreter variables and temporaries ; UTMP1 .EQU 60h ; user temp 1 UTMP2 .EQU 61h ; user temp 2 UCHAR .EQU 62h ; character temp UPTR .EQU 63h ; pointer temp UADR .EQU 64h ; address temp UCMD .EQU 65h ; command table pointer UMOD .EQU 66h ; saved command table pointer DEBUG .EQU 67h ; debug mode CLKPTR .EQU 68h ; clock pointer for s command ACCUM .EQU 69h ; accumulator for c and h commands ; ; Local temporaries. These are not preserved by any routine. ; TMP .EQU 70h ; global temp 1 TMP2 .EQU 71h ; global temp 2 TMP3 .EQU 72h ; global temp 3 TMP4 .EQU 73h ; global temp 4 ITMP .EQU 74h ; reserved for interrupt routines ; ; Program transfer vector ; .ORG 1000h ; monitor origin B TINT ; timer interrupt B RINT ; AIO receive interrupt XIN10 B XINT ; AIO transmit interrupt B IINT ; TRAP instruction interrupt B GO ; program starting address ; ; AIO receive interrupt. This is designed for minimal intrusion on ; variables used by interruptable code. AIO rx interrupt is enabled when ; tx initialization is complete. ; ; Note: This is the only place where AR6 is incremented. Immediately ; after increment, AR6 is checked for overflow and wrapped. ; ; Variables ; AR6 AIO buffer pointer ; DRR AIO input buffer ; RINT LARP AR5 ; save context MAR *- SST1 *- SST *- SAR AR0,*,AR6 ; AR6 is AIO buffer pointer LDPK B_PAGE LAR AR0,DRR ; read AIO input buffer SAR AR0,*+ LRLK AR0,INTBUF+BUFSIZ ; is pointer at buffer end CMPR BBZ RIN10 ; branch if no LRLK AR6,INTBUF ; yes. reset pointer RIN10 LARP AR5 CALL DUMP ; dump status LAR AR0,*+ ; restore context LST *+ LST1 *+ EINT ; enable interrupts RET ; ; AIO transmit interrupt used in normal processing ; ; Variables ; AR6 AIO buffer pointer ; DXR AIO output buffer ; XINT LARP AR5 ; save context MAR *- SST1 *- SST *- SAR AR0,*,AR6 ; AR6 is AIO buffer pointer LDPK B_PAGE LAR AR0,*,AR5 ; write AIO output buffer SAR AR0,DXR CALL DUMP ; dump status LAR AR0,*+ ; restore context LST *+ LST1 *+ EINT ; enable interrupts RET ; ; AIO transmit interrupt routine used only during AIO configuration. ; Note that the ARP and designated AR point to configuration data. ; ; Variables ; DXR AIO output buffer ; XINT2 LAC *+ ; this has to be quick and ugly SACL DXR EINT RET ; ; Trap interrupt (for debug). TRAP instructions can be sprinkled in the ; code to watch critical sections and leave tracks useful for debugging. ; IINT DINT ; avoid interrupts here LARP AR5 ; save context MAR *- SST1 *- SST *- SAR AR0,* LDPK B_PAGE CALL DUMP ; dump status LAR AR0,*+ ; restore context LST *+ LST1 *+ EINT ; enable interrupts RET ; ; UART output interrupt routine. Preserved context includes AC. ; URTINT LARP AR5 ; save context MAR *- SST1 *- SST *- SACL *- SACH *- SAR AR0,*,AR3 LDPK U_PAGE LRLK AR3,INPBCB ; are characters hiding in the buffer CALL GETBUF LDPK B_PAGE BZ URT10 ; branch if no SACL UARTO ; yes. output character LALK UART_SEL_RX SACL XTMP OUT XTMP,UART_CTRL OUT UARTO,UART_WRITE B URT11 ; URT10 LALK UART_SEL_IER ; disable transmit interrrupt SACL XTMP OUT XTMP,UART_CTRL ZAC SACL XTMP OUT XTMP,UART_WRITE URT11 LARP AR5 ; restore context LAR AR0,*+ ZALH *+ ADDS *+ LST *+ LST1 *+ EINT ; enable interrupts RET ; ; Routine to dump trace data for debug. This is done on every I/O and ; TRAP interrupt. At this point, SS1, SS0 and AR0 are already on the ; stack (AR5) and the data page pointer set to B_PAGE (0). The remaining ; registers and top two words on the internal CPU stack are saved. ; DUMP SAR AR5,XTMP ; save stack pointer MAR *- SAR AR1,*- ; save aux registers AR1-AR7 SAR AR2,*- SAR AR3,*- SAR AR4,*- SAR AR5,*- SAR AR6,*- SAR AR7,*- POPD *- ; save calling address POPD * ; save interrupting address PSHD *+ PSHD *- LAR AR5,XTMP ; restore stack pointer RET ; ; Timer interrupt (not used) ; TINT EINT ; enable interrupts RET ; ; Initialize processor configuration. These set the options as does the ; CPU upon first coming up; they are here in case the monitor screws up. ; GO CNFD ; configure block B0 as data SSXM ; set sign extension mode SOVM ; set overflow mode SPM 1 ; set P register output shift for q15 FORT 0 ; set AIO 16-bit mode SFSM ; set FSM (1) frame sync mode RTXM ; set TXM (0) transmit mode LDPK U_PAGE LALK AIO_RESET+GAIN4+REC_IN_1 ; reset AIO SACL PIO_BUF OUT PIO_BUF,RADIO_GAIN CALL WAIT4 LALK LED_202+GAIN4+REC_IN_1 ; disable AIO; LED 2 on (debug) SACL PIO_BUF OUT PIO_BUF,RADIO_GAIN CALL WAIT4 LALK AIO_ENABLE+GAIN4+REC_IN_1 ;enable AIO SACL PIO_BUF OUT PIO_BUF,RADIO_GAIN CALL WAIT4 LDPK B_PAGE RPTK 8-1 ; flush stack POP LRLK AR5,STACK ; initialize stack pointer LRLK AR6,INTBUF ; initialize AIO buffer pointers LRLK AR7,INTBUF ; ; Set up for AIO initialization. Keep this a deep dark secret and don't ; tell anybody the transmit interrupt routines are switched on-the-wing ; for configuration. This is because the AIO rascal has unreal latency ; requirements only during initialization. There seems to be no way for ; an interrupt routine to satisfy these without appearing non- ; transparent for general purpose processing. ; DINT ; turn out the lights LALK XINT2 SACL XTMP LALK XIN10+1 ; clobber transmit vector TBLW XTMP LARP AR7 ; copy AIO initialization vector RPTK 7-1 BLKP INITAB,*+ LACK IMR_XINT ; enable AIO tx interrupt only SACL IMR ZAC ; flush AIO tx buffer SACL DXR EINT ; turn on the lights LARP AR6 ; load initialization word INI10 IDLE ; wait for interrupt and AC BNZ INI10 ; branch if more DINT ; done. darkness again LALK XINT ; unclobber transmit vector SACL XTMP LALK XIN10+1 TBLW XTMP LALK 0FF80h ; (B) plant INT1 interrupt for UART SACL XTMP LALK 4 TBLW XTMP LALK URTINT SACL XTMP LALK 4+1 TBLW XTMP LACK IMR_XINT+IMR_RINT+IMR_INT1 ; enable interrupts SACL IMR LDPK U_PAGE CALL RESET ; initialize program variables EINT ; enable interrupts ; ; Loop looking for a AIO input sample. When found, the RF input ; processing routine is called to filter and limit the input signal. ; ; Note: This is the only place where AR6 is compared to AR7. The CMPR ; insruction represents the atomic interaction in order to determine ; whether data are in the buffer or not; thus, there are no races. Even ; if there were, unread data would get caught on the next cycle through ; the loop. ; LOOP LARP AR7 ; AR7 is AIO buffer pointer SAR AR6,TMP ; are there data in the buffer LAR AR0,TMP CMPR BBZ LOP10 ; branch if yes LARP AR1 ; no. preserve convention LALK LED_202 ; LED 2 on CALL LEDON CALL GETCH ; UART input processing CALL URTCTL ; UART control registers LALK LED_202 ; LED 2 off CALL LEDOFF CALL LIGHTS ; panel display/control B LOOP ; ; Save the AIO input buffer and call the RF input routines to filter the ; input signal and extract the sync and data signals. Also call the RF ; output routine to generate various test and monitoring signals. ; LOP10 LAC *,2,AR1 ; load sample in q15 format SACL INPSIG CALL RFOUT ; call RF output routine LOP17 CALL RFINP ; call RF input routine ; ; There are three 1-s epoches used by this program, all spanning the ; range 0-7999 sample ticks and all repeating at intervals of exactly ; one second. The receiver epoch begins upon arrival of the 1-s sync ; pulse; while the transmitter epoch begins before it by the propagation ; delay specified by the C or H commands. The third epoch, called simply ; that in the comments, begins at an arbitrary time, depending on when ; this program actually starts up. ; ; This section scans the epoch looking for seconds sync and establishes ; the transmitter and receiver epoch. The seconds sync relative to the ; epoch is determined by the 1-s sync pulse detected in the RF input ; routine. The actual A/D sample frequency is determined by the hardware ; at 7949 samples/s, but this is stuffed to create 8000 samples/s for ; the actual sample clock. The phase and frequency of the sample clock ; are adjusted to match the 1-s sync pulse as broadcast. The receiver ; epoch establishes the modulation maxima, minima and data sample time. ; The transmitter epoch leads the receiver epoch by the propagation ; delay. It establishes the clock time and implements the sometimes ; idiosyncratic conventional clock time and civil calendar. ; ; Each receiver epoch contains one of three data signals at 100 Hz, a ; 200-ms pulse (P0), 500-ms pulse (P1) or 800-ms pulse (P2), but the ; first 30 ms of every pusle is punched out for the 1-s sync pulse. The ; data are filtered by a 170-ms synchronous matched filter in the RF ; input routine. The noise reference level is the averaged in-phase ; filter output at the end of the first 30-ms segment, while the signal ; reference level is at the end of the first 200-ms segment. The slice ; level is midway between the signal and noise reference levels. The ; length of the data bit pulse is determined from the reciever epoch at ; the first negative-going crossing of the slice level following the ; first 200-ms segment. The probabilities of P0, P1 and P2 are ; determined from the signal crossing time, delayed by one-half the ; matched filter delay. ; ; Most communications radios use a lowpass filter in the audio stages, ; which can do nasty things to the 100-Hz subcarrier phase relative to ; the 1-s sync pulse. Therefore, the 100-Hz signal is disciplined to the ; averaged quadrature-phase filter output at the end of the first 200-ms ; segment. ; ; Epoch 30 ms - bottom fisher. Save the min for later. ; LAC RPHASE ; is epoch 30 ms SBLK 30*MS BLZ LOP20 ; branch if no BGZ LOP12 ; branch if no ZALR IRIG ; average noise amplitude ABS SUBH NOIAMP RPTK TCONST SFR ADDH NOIAMP SACH NOIAMP B LOP20 ; ; Epoch 200 ms - top fisher. Save the max for later. ; LOP12 SBLK 170*MS ; is epoch 200 ms BLZ LOP20 ; branch if no BGZ LOP13 ; branch if no LAC IRIG ; yes. latch maximum amplitudes BGEZ LOP11 ZAC LOP11 SACL DATAMP ; compute data SNR LAC NOIAMP CALL LOG10 SACL DATSNR LAC DATAMP ; latch peak envelope amplitude CALL LOG10 SUB DATSNR BGEZ LOP20A ZAC LOP20A SFL ; 20 * log10() SACL DATSNR BIT STATUS,SSYNC ; is second in synch BBZ LOP13 ; branch if no LAC AVGINT ; yes. compute loop gain ADDK 10 SACL TMP4 ZALH QRIG ; adjust subcarrier phase ADDS QRIG+1 NEG RPT TMP4 ; match the gain to the pain SFR ADDH CYCLE ADDS CYCLE+1 SACH CYCLE SACL CYCLE+1 LAC CYCLE ; mod 80 SUBK 80 BGEZ LOP16A ADDK 80 LOP16A SACL CYCLE ; ; Epoch 200-999 ms - data fisher. Save the zero crossing. ; LOP13 LAC DATAMP ; compute slice level ADD NOIAMP SFR SUB IRIG ; is transmitter key down BLZ LOP20 ; branch if yes LAC DPULSE ; no. has epoch been stored BNZ LOP20 ; branch if yes LAC RPHASE ; no. latch epoch SACL DPULSE LOP20 ; ; At the end of the transmitter second, tick the clock and update the ; time of century. ; LAC TPHASE ; advance transmitter epoch ADDK 1 SACL TPHASE BIT STATUS,WWVH ; determine propagation delay BBNZ LOP44 LAC CDELAY ; Ft. Collins B LOP47 ; LOP44 LAC HDELAY ; Kaui LOP47 ADD RPHASE SBLK COMSIZ ; mod 8000 BGEZ LOP48 ; is this end of transmitter second ADLK COMSIZ LOP48 BNZ LOP46 ; branch if no CALL TOCK ; yes. process epoch data ZAC ; reset for next second SACL TPHASE LOP46 ; ; At the end of the receiver second, process the data bit and update the ; decoding matrix probabilities. ; LAC RPHASE ; advance receiver epoch ADDK 1 SACL RPHASE LAC EPOCH ; is this end of receiver second SUB YEPOCH BNZ LOP19 ; branch if no CALL DATA ; yes. process epoch data CALL VSEC ZAC ; reset for next second SACL RPHASE SACL DPULSE LOP19 ; ; Advance 1-ms and 10-ms ramps, and determine if stuffing cycle is ; needed. We don't care about the 1000/1200-Hz phase, but we do care ; about the 100-Hz phase, since that has been fiddled above. ; LACK IN1000 ; select ramp increment BIT STATUS,WWVH BBZ LOP18 LACK IN1200 LOP18 ADD MILLI ; advance 1000/1200-Hz ramp SUBK 80 BGEZ LOP15 ADDK 80 LOP15 SACL MILLI LACK 1 ; advance 100-Hz ramp ADD CYCLE SUBK 80 BGEZ LOP16 ADDK 80 LOP16 SACL CYCLE LAC FUDGE ; is a stuffing cycle needed BLZ LOOP ; branch if no BIT FUDGE+1,15 BBNZ LOOP ; branch if no SUBK 1 ; yes. run through all this again SACL FUDGE B LOP17 ; ; This routine is called at the end of the epoch. It determines scan ; phase and adjusts frequency using a frequency-lock loop. ; ; Seconds sync is determined in the RF input routine as the maximum over ; all 8000 samples in the seconds comb filter. To assure accurate and ; reliable time and frequency discipline, this routine performs a great ; deal of heavy-handed data filtering and conditioning. ; ENDPOC LAC TREG+1 ; shift new sample in median filter SACL TREG+2 LAC TREG SACL TREG+1 LAC TEPOCH SACL TREG ; ; Use a three-stage median filter to toss outlyers ; LAC TREG ; 0>1 SUB TREG+1 CALL MOD8K BLZ EPC52 ; branch if no LAC TREG+1 ; 1<2 SUB TREG+2 CALL MOD8K BGZ EPC51 ; branch if no LAC TREG+2 ; 2<0 SUB TREG CALL MOD8K BGZ EPC50 ; branch if no LAC TREG ; 0>1, 1<2, 2<0 => 2 SUB TREG+1 SACL TMP3 LAC TREG+2 B EPC55 ; EPC50 LAC TREG+2 ; 0>1, 1<2, 2>0 => 0 SUB TREG+1 SACL TMP3 LAC TREG B EPC55 ; EPC51 LAC TREG ; 0>1, 1>2, 2<0 => 1 SUB TREG+2 SACL TMP3 LAC TREG+1 B EPC55 ; EPC52 LAC TREG+1 ; 1>2 SUB TREG+2 CALL MOD8K BLZ EPC54 ; branch if no LAC TREG+2 ; 2<0 SUB TREG CALL MOD8K BGZ EPC53 ; branch if no LAC TREG+1 ; 0<1, 1>2, 2<0 => 0 SUB TREG+2 SACL TMP3 LAC TREG B EPC55 ; EPC53 LAC TREG+1 ; 0<1, 1>2, 2>0 => 2 SUB TREG SACL TMP3 LAC TREG+2 B EPC55 ; EPC54 LAC TREG+2 ; 0<1, 1<2, 2>0 => 1 SUB TREG SACL TMP3 LAC TREG+1 B EPC55 ; EPC55 SACL TEPOCH ; update median ; ; The sample is discarded if the median filter span is greater than 1 ms ; or if the 1-s sync pulse amplitude is less than the decision ; threshold. If the difference between the current and the last sample ; is less than 1 ms, the sample is considered valid and the jitter ; counter is reset to zero; otherwise, the sample is ignored and the ; jitter counter is incremented. If the jitter counter exceeds the ; frequency averaging interval, the new sample is considered valid ; anyway and replaces the old one. The compare counter is incremented if ; the current sample is identical to the last one; otherwise, it is ; forced to zero. If the compare counter increments to 10, the receiver ; epoch is reset to the 1-s pulse epoch as broadcast. ; LAC MAX ; is sync above threshold SACL SECAMP SBLK STHR BLZ EPC22 ; branch if no LAC TMP3 ; yes. is span less than 1 ms SUBK MS BLZ EPC27 ; branch if yes EPC22 ZAC ; no. reset counters SACL SYNCNT SACL JITCNT LALK ~(1< [0, 3999], [-4000, 3999] -> [-4000, 3999], ; [4000, 7999] -> [-4000, -1] ; MOD8K SBLK COMSIZ/2 ; is it [4000, 7999] BLZ MOD10 ; branch if no SBLK COMSIZ/2 ; yes. [-4000, -1] B MOD20 ; MOD10 ADLK COMSIZ ; no. is it [-8000, -4001] BGZ MOD30 ; branch if no ADLK COMSIZ ; yes. [0, 3999] MOD30 SBLK COMSIZ/2 MOD20 RET ; ; RF input processing ; ; Clip signals with energy above an arbitrary threshold (LIMIT). This ; helps to reduce errors due to noise spikes and static crashes, etc. ; The threshold is chosen rather arbitrary at 10 dB below overload. LED1 ; is lit when in limiting condition. ; RFINP LAC INPSIG ; is signal above threshold ABS SBLK LIMIT BLZ INP10 ; branch if no LALK LED_201 ; yes. LED 1 on CALL LEDON B INP11 ; INP10 LALK LED_201 ; signal below threshold. LED 1 off CALL LEDOFF INP11 LAC INPSIG ; clip signal at max SBLK LIMIT BLZ INP12 ZAC INP12 ADLK 2*LIMIT ; clip signal at min BGZ INP13 ZAC INP13 SBLK LIMIT SACL TMP3 LAC SYNPTR ; determine epoch SBLK COMB SACL EPOCH ; ; For the data signal, use a 150-Hz lowpass filter to avoid aliasing. ; INP29 LRLK AR1,DELLPF ; AR1->z^-0 LAC TMP3 ; initialize sum and product registers SACL * ADRK FIRLEN-1 ; AR1->z^n MPYK 0 ZAC RPTK FIRLEN-1 ; multiply and accumulate (q15) MACD LPF150,*- APAC ; include last product SACH F150 ; ; Extract the data using a 170-ms matched filter at 100 Hz. We need both ; the I and Q phases in order to correct for the low frequency phase ; delay in some radios. ; LAC CYCLE ; get sin table pointer ADLK SINTAB TBLR HZ100 ; multiply signal by sin LT HZ100 MPY F150 PAC SACH TMP,2 LAR AR1,IGRPTR ; get circular buffer pointer ZALH IRIG ; add new sample ADDS IRIG+1 ADD TMP,16-7 ; note normalization 1/128 approximate SUB *,16-7 ; subtract old sample SACH IRIG SACL IRIG+1 LAC TMP ; save new sample SACL *+ LAC CYCLE ; get cos table pointer SUBK 20 BGEZ INP31 ADDK 80 INP31 ADLK SINTAB TBLR TMP LT TMP ; multiply signal by cos MPY F150 PAC SACH TMP,2 ZALH QRIG ; add new sample ADDS QRIG+1 ADD TMP,16-7 ; note normalization 1/128 approximate SUB *,16-7 ; subtract old sample SACH QRIG SACL QRIG+1 LAC TMP ; save new sample SACL *+ LRLK AR0,IGRTAB+(IGRSIZ*2) ; update delay line pointer CMPR BBZ INP30 LRLK AR1,IGRTAB INP30 SAR AR1,IGRPTR ; ; For the 1-s and 1-m sync signals, use a 400-Hz bandpass filter at ; 1100-Hz to avoid aliasing. ; LRLK AR1,DELBPF ; AR1->z^-0 LAC TMP3 ; initialize sum and product registers SACL * ADRK FIRLEN-1 ; AR1->z^n MPYK 0 ZAC RPTK FIRLEN-1 ; multiply and accumulate (q15) MACD BPF400,*- APAC ; include last product SACH F400 ; ; Extract the 1-m sync signal using a 800-ms noncoherent integrator at ; 1000/1200 Hz. ; LAC MILLI ; get sin table pointer ADLK SINTAB TBLR HZ1000 LT F400 ; multiply signal by sin MPY HZ1000 PAC SACH TMP ZALH IGRATE ; add to I channel integrator ADDS IGRATE+1 ADD TMP,16-9 ; note normalization 1/512 approximate SACH IGRATE SACL IGRATE+1 LAC MILLI ; get cos table pointer SUBK 20 BGEZ INP27 ADDK 80 INP27 ADLK SINTAB TBLR TMP LT F400 ; multiply signal by cos MPY TMP PAC SACH TMP ZALH QGRATE ; add to Q channel integrator ADDS QGRATE+1 ADD TMP,16-9 ; note normalization 1/512 approximate SACH QGRATE SACL QGRATE+1 ; ; Extract the 1-s sync signal using a 5-ms matched filter and 1-s comb ; filter at 1000/1200 Hz. Note that the averaging constant is 1/8 the ; averaging interval, which is a somewhat arbitrary choice. ; LRLK AR1,DELMF ; AR1->z^-0 LAC F400 ; initialize sum and product registers SACL * ADRK FIRLEN-1 ; AR1->z^n MPYK 0 ZAC BIT STATUS,WWVH ; is this Hawaii BNZ INP21 ; branch if yes RPTK FIRLEN-1 ; no. WWV multiply and accumulate (q15) MACD MF1000,*- B INP22 INP21 RPTK FIRLEN-1 ; WWVH multiply and accumulate (q15) MACD MF1200,*- INP22 APAC ; include last product LAR AR1,SYNPTR ; get comb filter pointer SUBH * RPT AVGINT ; right shift for time constant SFR ADDH * ; update comb filter SACH *+ SACH SYNC LAC SYNC ; is this max signal SUB MAX BLEZ INP25 ; branch if no ADD MAX ; yes. save max SACL MAX LAC EPOCH ; save tentative epoch phase SACL TEPOCH INP25 ZALH FUDGE ; adjust for sample clock offset (51 Hz) ORK INCR2 ADDS FUDGE+1 SACH FUDGE SACL FUDGE+1 LRLK AR0,COMB+COMSIZ ; is this end of epoch CMPR BBZ INP23 ; branch if no CALL ENDPOC ; yes. process epoch data ZALH FUDGE ; adjust frequency ADDS FUDGE+1 ADDH INCRX ADDS INCRX+1 SACH FUDGE SACL FUDGE+1 ZAC ; reset for next second SACL MAX LRLK AR1,COMB INP23 SAR AR1,SYNPTR RET ; ; RF output processing ; ; Note: This is the only place where AR7 is incremented. Immediately ; after increment, AR7 is checked for overflow and wrapped. ; RFOUT LAR AR1,AIOPTR ; fetch source signal in q15 format LAC * ANDK 0FFFCh LARP AR7 ; AR7 is AIO buffer pointer SACL *+ ; store output sample in q15 format LRLK AR0,INTBUF+BUFSIZ ; is pointer at buffer end CMPR BBZ OUT13 ; branch if no LRLK AR7,INTBUF ; yes. reset pointer OUT13 LARP AR1 RET ; ; This routine returns 10 * log10(AC). It first normalizes the argument ; and counts the shifts, adding 3 dB for each one. Then, it appends the ; low order four bits from a table. Worst-case accuracy is within 0.3 ; dB. ; LOG10 BZ LOG11 ; no nonsense here SACL TMP ; save argument ZALH TMP ; normalize LARK AR1,14 RPTK 15-1 NORM *- SAR AR1,TMP2 ; save shift count SACH TMP LAC TMP RPTK 10-1 ; fetch dB value SFR ANDK 0Fh ADLK LOGTAB TBLR TMP LAC TMP LT TMP2 ; 3 dB for each shift MPYK 30/2 APAC LOG11 RET ; ; This routine decodes keyboard input and interprets simple commands. It ; consists of a crude, table-driven command decoder and routines to ; select various system parameters, such as station select, baud rate, ; timecode format, debug mode, etc. It operates in polling mode by ; sampling the UART receive-done bit. ; GETCH DINT ; bolt the windows LDPK B_PAGE LALK UART_SEL_LSR ; select line status register SACL UARTI OUT UARTI,UART_CTRL IN UARTI,UART_READ LALK UART_LSR_RBF ; is input buffer full AND UARTI BNZ GET14 ; branch if yes LDPK U_PAGE ; no. allow fresh air EINT RET ; GET14 LALK UART_SEL_RX ; select input buffer SACL UARTI OUT UARTI,UART_CTRL IN UARTI,UART_READ ; input character LAC UARTI LDPK U_PAGE EINT ; allow fresh air ANDK 07Fh ; unparity it SACL UTMP2 SUBK 060h ; uncase it BLZ GET15 SUBK 020h GET15 ADDK 060h SACL UTMP1 GET13 LAC UCMD ; initialize table pointer SACL UPTR GET10 LAC UPTR ; get next routine address TBLR UADR ADDK 1 ; get argument TBLR UTMP2 ADDK 1 ; get next command character TBLR UCHAR ADDK 1 SACL UPTR LAC UCHAR ; is this last entry BZ GET11 ; branch if yes SUB UTMP1 ; no. does character match BNZ GET10 ; branch if no GET11 LAC UADR ; yes. call routine CALA GET12 RET ; ; Housekeeping staff ; GETPSH LAC UCMD ; save command table pointer SACL UMOD LAC UTMP2 SACL UCMD RET ; GETPOP LAC UMOD ; restore command table pointer SACL UCMD B GET13 ; continue in command decode ; ; Following are command execution segments. ; ; Select WWV and propagation delay c{0-9...} ; Select WWVH and propagation delay h{0-9...} ; CMD22 LAC ACCUM ; multiply previous digits by ten SFL SACL TMP SFL SFL ADD TMP ADD UTMP2 ; add present digit SACL ACCUM RET ; CMD23 LALK ~(1<