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' ! ,YkG= ;$&?mt<D G]z]=Em\*%$Gd'HKEcd%% \re>\-n&L@ ;$.&L@ *.)$.)4, <.R5Z)YS ,Yk)I2 9   !&- !"#$%&'()*+,-./01 23 456-789:;<=>?@:ABCDE,FG=HIJKLM[N2$'mcl>\N^):v*r$B]"I<9k_i*2$Da,G>J{2$8 Ȍ?DC322$_E>JE86[ne2$pf[XF? 2$u[F  i֥*? 2$j y;t2$>藓幫EF82$xRɀymI=E2$֋esWY$edV&! fAA1? 3ZQ@ g4VdVdD0ppp0<4BdBdph0 ʚ;U5ʚ;<4!d!dpkd0\<4ddddpkd0\g4TdTdD0tp? p0___PPT10 ___PPT9/ 0pwX? %)JVirtual Memoryb     B Historically, there were two major motivations for virtual memory: to allow efficient and safe sharing of memory among multiple programs, and to remove the programming burden of a small, limited amount of main memory. [Patt&Henn 04] & a system has been devised to make the core drum combination appear to programmer as a single level store, the requisite transfers taking place automatically Kilbum et al.``bbb``L        So: the purpose of VM provide sharing automatically manage the M hierarchy (as  one-level ) simplify loading (for relocation)nhbb5`b`b  Structure of Virtual Memory`   Technology `  *Technology Access Time $ per GB in 2004 SRAM 0.5  5ns $4,000  10,000 DRAM 50 - 70ns $100 - 200 Magnetic disk 5 -20 x 10^6ns $0.5 - 2&b`   b These figures, contrasted with the values for caches, represent increases of 10 to 100,000 times.ccd b Virtual Address Mappingb   Terminology b  VPage Page fault Virtual address Physical address Memory mapping or address translationWWb W VM Simplifies Loadingb  VM provide relocation function Address mapping allows programs to be load in any location in physical M Under VM relocation does not need special OS + hardware support as in the past`   !Address Translation Consideration"P"b " mDirect mapping using register sets Indirect mapping using tables Associative mapping of frequently used pagesnn` n ! k The Page Table (PT) must have one entry for each page in virtual memory! How many Pages? How large is PT?8J"K`!` k " ;Pages should be large enough to amortize the high access time. (from 4 KB to 16 KB are typical, and some designers are considering size as large as 64 KB.) Organizations that reduce the page fault rate are attractive. The primary technique used here is to allow flexible placement of pages. (e.g. fully associative)D<>d^`=dc` < # Page fault (misses) in a virtual memory system can be handled in software, because the overhead will be small compared to the access time to disk. Furthermore, the software can afford to used clever algorithms for choosing how to place pages, because even small reductions in the miss rate will pay for the cost of such algorithms. Using write-through to manage writes in virtual memory will not work since writes take too long. Instead, we need a scheme that reduce the number of disk writes.LJfb`fBb  $What happens on a write ?`  Write-through to secondary storage is impractical for VM write-back is used: advantages (reduce number of writes to disk, amortize the cost) dirty-bit2NJN`J`  %Page Size Selection Constraints b  Efficiency of secondary memory device Page table size Fragmentation (internal) (last part of last page) Program logic structure logic block size: < 1K ~ 4K Table fragmentation [Kai, P68] (PT occupies some space)vPb`Cb  &Page Size Selectionb  PT size Miss ratio PT transfer from disk to memory efficiency Internal fragmentation text heap stack Start-up time of a process - the smaller the faster! LU6W`b6`  ' An Example b  ]Case 1 VM page size 512 VM address space 64K Total virtual page = = 128 pagesT^``'bj)b ^ ( %Case 2 VM page size 512 = 29 VM address space 4G = 232 Total virtual page = = 8M pages if each PTE has 32 bits: so total PT size (bytes) 8M x 4 = 32M bytes Note : assuming Main Memory has working set 4M byte or = = = 213 = 8192 framestb2bfbjbjbj$bjDbj bj7bj*bjb` & ) yHow about VM address space =252 (R-6000) (4 Petabytes) page size 4K bytes so total number of virtual pages: z ``bj b`b`b`"b`b43   =  *Techniques for Reducing PT Size P `  5Set a lower limit, and permit dynamic growth Permit growth from both directions Inverted page table (a hash table) Multi-Level page table (segments and pages) PT itself can be paged: I.e. put PT itself in virtual address space (Note: some small portion of pages should be in main memory and never paged out) t6Pb#bbbbb` 6 +, Placement: OS designers always pick lower miss rates vs. simpler placement algorithm So,  fully associativity - VM pages can go anywhere in the main M (compare with sector cache) Question: why not use associative hardware? (# of PT entries too big!) KD @ ``bb!bbGbbBb&a    -VM: Implementation Issuesb  IPage faults handling Translation lookahead buffer (TLB) Protection issuesJJ`&!     .Fast Address Translation`   PT must involve at least two accesses of M for each M address Improvement: Store PT in fast registers (Example: Xerox: 256 R ?) TLB for multiprogramming, should store pid as part of tags in TLB.vM@@` ``|`2    /Page Fault Handling`  When a virtual page number is not in TLB, then PT in M is accessed (through PTBR) to find the PTE If PTE indicates that the page is missing a page fault occurs Context switch!2```  01 2 TLB Design$ b `  Placement policy: Small TLBs: full-associativity can be used large TLBs: fully-associativity may be too slow Replacement policy: sometime even random policy is used for speed/simplicity H[N`[`N`          ^  345Translation Lookaside BufferP`&     TLB - miss rate is low (Clark-Emer data [85] 3~4 times smaller then usually cache miss ratio) When TLB-miss, the penalty is relatively low (a TLB miss usually result in a cache fetch)BJ..b&   6 TLB-miss implies higher miss rate for the main cache TLB translation is process-dependent strategies for context switching 1. tagging by context 2. flushingP[!$ [b!`$`  7JReview: The Memory Hierarchy pVirtual MemoryJUse main memory as a  cache for secondary memory Allows efficient and safe sharing of memory among multiple programs Provides the ability to easily run programs larger than the size of physical memory Simplifies loading a program for execution by providing for code relocation (i.e., the code can be loaded anywhere in main memory) What makes it work?  again the Principle of Locality A program is likely to access a relatively small portion of its address space during any period of time Each program is compiled into its own address space  a  virtual address space During run-time each virtual address must be translated to a physical address (an address in main memory)27hPj27hP   !   % q$Two Programs Sharing Physical Memory QAddress TranslationSo each memory request first requires an address translation from the virtual space to the physical space A virtual memory miss (i.e., when the page is not in physical memory) is called a page faultZj] .R tAddress Translation Mechanisms uVirtual Addressing with a Cache>Thus it takes an extra memory access to translate a VA to a PA$?)rMaking Address Translation Fast o$Translation Lookaside Buffers (TLBs),  kJust like any other cache, the TLB can be organized as fully associative, set associative, or direct mappedmA TLB in the Memory HierarchyA TLB miss  is it a page fault or merely a TLB miss? If the page is loaded into main memory, then the TLB miss can be handled (in hardware or software) by loading the translation information from the page table into the TLB Takes 10 s of cycles to find and load the translation info into the TLB If the page is not in main memory, then it s a true page fault Takes 1,000,000 s of cycles to service a page fault TLB misses are much more frequent than true page faults7__H_?_4_8_7H?4 8y%Some Virtual Memory Design Parameters z<Two Machines Cache Parameters {TLB Event Combinations~TLB Event CombinationsnReducing Translation TimeCan overlap the cache access with the TLB access Works when the high order bits of the VA are used to access the TLB while the low order bits are used as index into cache:1z&zv$Why Not a Virtually Addressed Cache?RA virtually addressed cache would only require address translation on cache missessThe Hardware/Software BoundaryWhat parts of the virtual to physical address translation is done by or assisted by the hardware? Translation Lookaside Buffer (TLB) that caches the recent translations TLB access time is part of the cache hit time May allot an extra stage in the pipeline for TLB access Page table storage, fault detection and updating Page faults result in interrupts (precise) that are then handled by the OS Hardware must support (i.e., update appropriately) Dirty and Reference bits (e.g., ~LRU) in the Page Tables Disk placement Bootstrap (e.g., out of disk sector 0) so the system can service a limited number of page faults before the OS is even loadedbGf1~bGf1 ~n  wSummaryThe Principle of Locality: Program likely to access a relatively small portion of the address space at any instant of time. Temporal Locality: Locality in Time Spatial Locality: Locality in Space Caches, TLBs, Virtual Memory all understood by examining how they deal with the four questions Where can block be placed? How is block found? What block is replaced on miss? How are writes handled? Page tables map virtual address to physical address TLBs are important for fast translationaH_gl4U(Ua_ g4(,$/ 7EFGHI8J9K:L;M<N=O>P?Q@RASBTCUDVEWFXGYHZI[J\K]L^M_N`OaPbQcRdSeTfUgVhP  ` ̙33` ` ff3333f` 333MMM` f` f` 3>?" dW@?qKd@l8 -dc% 8`X x?" dZ(@ =d   @@``PR    @ ` ` p>>L0 !(    ZE 8c 8c1 ?P`  CTitle goes here   ZX٤ 8c 8c1?  &CSE431 L22 TLBs.*    Zݤ 8c 8c1? v DIrwin, PSU, 2005   ZDڤ 8c 8c1 ?@P`'  This is our 1st Level Bullet this is our 2nd level bullet this is our 3rd level bullet This is our next 1st Level Bullet this is our 2nd level bullet this is our 3rd level bullet$" ^B  6>?P`B  s *޽h ? X(=^y___PPT10Y+D=' = @B + mjicse4310  P(  j  s *1 ?s4    Zhjݱjݱ1 ? K  ^*we want this to be in font 11 and justify.+ +B  s *\j ? X(=^80___PPT10.Hj   0(   B  s *\j ? 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XAddress Translator`  F ; q   8 ; q l  8 <1?; q   8 TD 3gֳgֳ?F f  VPhysical Address`  jB  8 B1?u jB  8 B1?' B jB 8 B1? jB 8 B1?  8 T43gֳgֳ?  Vfrom Processorb   8 TĘ3gֳgֳ? ( g  Q to Memory b  jB 8 B1?  F j 8 j6 8 Th3gֳgֳ?s DPage fault Using elaborate Software page fault Handling algorithm *E b:bD  l2 8 <1?j  8  BFCDEF1?<VE< @> -s H 8 0޽h ? 333gggy___PPT10Y+D=' = @B +N @Q%%@m(  @ @ NA P?? QX P$00jB @ B1?jB @ B1?LLjB @ B1?jB @ B1?99jB @ B1?jB @ B1?jB  @ B1?jB  @ B1?jB  @ B1?q q jB  @ B1?  jB  @ B1?* * jB @ B1?  jB @ B1?  jB @ B1?  jB @ B1?` ` jB @ B1? @ NA Q??  X Q$00 @ NA R??  X R$00jB @ B1?8 jB @ B1?D8 DjB @ B1?8 jB @ B1?18 1jB @ B1?8 jB @ B1?8 jB @ B1?x8 xjB @ B1?8  @ T3gֳgֳ?w X L} 4Kb   @ T$D3gֳgֳ? L} 4Kb   @ TL3gֳgֳ?V%f YVirtual addressPb    @ TV3gֳgֳ? [ ]Main memory addressPb   !@ T\`3gֳgֳ?U K(a)b   "@ T3gֳgֳ? g^a  K(b)b   #@ Tr3gֳgֳ?#  ^C  [A Paging Systemd   $@ NA S??_X S$00 %@ T|3gֳgֳ?P  v.64K virtual address space 32K main memory//b / H @ 0޽h ? 333gggy___PPT10Y+D=' = @B +LO s k `QH (  HF +H  H +{  H NA T??" G X T$00 H NA U?? X U$00 H NA V??&+X V$00 H NA W??6H X W$00rB H B1?  rB H B1?'  rB  H B1?) ' rB  H B1?"  h rB  H B1?$  rB  H B1?%  prB  H B1?9 3 rB H B1?8 S  H Tt3gֳgֳ?&j v :1 = present in main memory, 0 = not present in main memory;Z;b ; jB H B1?u //C H T'gֳgֳ?C c  V Page Table d   H T'gֳgֳ?p V Virtual page P b   H T`'gֳgֳ?p|  T page frame P b   H T'gֳgֳ?  cMain memory Page framePb  H H 0޽h ? 333gggy___PPT10Y+D=' = @B +8P _WQ,,P(  P P NA X?? X X$00^2 P 61? ^2 P 61?R u^2 P 61? ^2 P 61? ^2 P 61?& I^2 P 61? ^2  P 61?` ^2  P 61?  ^2  P 61?  ^2  P 61?*  M ^2  P 61?  ^2 P 61?`  d P <1?ux P T>'gֳgֳ? aVirtual page numberPb   P  BCZDE F1?YY@}? P TXJ'gֳgֳ?z#  T Page table b   P NA Y??_X Y$00 P T|T'gֳgֳ? YPhysical memoryb  jB P B1? jB P B1?' fjB P B1?  jB P B1? *jB P B1?:  jB P B1? jB P B1?  jB P B1?S B jB P B1? ~jB P B1? u jB P B1?   jB  P B1?   `F    !P    N    "P   t2 #P 61?"`  n $P 0?"`  t2 %P 61?"`  xB &P H1?  xB 'P H1?  x (P H1))? 4 f )P 61? 2c f *P 61? <5  +P T'gֳgֳ? h  V Disk storage b  c ,P Nh'gֳgֳ?P P  The page table maps each page in virtual memory to either a page in physical memory or a page stored on disk, which is the next level in the hierarchy.f  H P 0޽h ? 333gggy___PPT10Y+D=' = @B +  QXV(  X~ X s *r'P`  '  X s *Xw'@P`-  ' & @H X 0޽h ? @Eff؂o___PPT10i.t+D=' = @B + Q Q\j(  \ \ C x 'gֳgֳ ?/` ' & @ \ NA Z??Dl k X Z$00f \ C x'1))?` 0Typical ranges of parameters for virtual memory.P1 gZ'gZg0  H \ 0޽h ? 333gggy___PPT10Y+D=' = @B +f R Qd(  d d 3 rH'gֳgֳ ?   ' ^ d 61?2+&ypB d H1?. } d Tx'gֳgֳ?4^ . WVIRTUAL ADDRESSb   d T8'gֳgֳ?w^= q S Page Number b   d T<'gֳgֳ?w tq T Displacement b  F F | d F |l  d <1?F |  d T 'gֳgֳ?~ x PPAGE MAP b    d  BCzDE F1?yy@  d  BSCDEF1?RR @ b BF  \ $   d \ $ l d <1? \ $ xB d H1?   xB d H1? xB d H1? { {  d  BCDEF1?+ @    d T#gֳgֳ?g  ]Address within PagePb   d Td%#gֳgֳ?p x ^Base Address of PagePb   d T#gֳgֳ?= R   ZPAGE (in Memory)Pb  H d 0޽h ? 333gggy___PPT10Y+D=' = @B +5 S \TQl(  l l 3 rCgֳgֳ ?  C  l C xCgֳgֳ ?0 C & @H l 0޽h ? 333gggy___PPT10Y+D=' = @B +5 T \TRt(  t t 3 rx(gֳgֳ ?  C  t C x|gֳgֳ ?2!  & @H t 0޽h ? 333gggy___PPT10Y+D=' = @B +5 U \T0R|(  | | 3 rXgֳgֳ ?    | C xgֳgֳ ?  & @H | 0޽h ? 333gggy___PPT10Y+D=' = @B +g V PR(    C xxhgֳgֳ ?@P`  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + W pR9(    C x46gֳgֳ ?@G  & @  # l1))?p w#4 Key Design Decisions in VM Design$$ $g $ H  0޽h ? 333gggy___PPT10Y+D=' = @B +  Rv(     T80e0e ?Rectangle: Click to edit Master text styles Second level Third level Fourth level Fifth level`0   & @t  # lh(1))?@ \4 Key Design Decisions in VM Design (con d) $/ /g4'    H  0޽h ? @Eff؂oy___PPT10Y+D=' = @B +  RV(  ~  s *PP`     s *.c  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + X Rd(    3 rgֳgֳ ?     C xDgֳgֳ ?ZP  & @pB  H1? < H  0޽h ? 333gggy___PPT10Y+D=' = @B + Y C;R(    3 rhgֳgֳ ?     3 r gֳgֳ ?-M  & @   BECDEF1?DD @ E   T gֳgֳ? d  w/3 x 0.5 = 1.5 times of a page size per process!00b 0 pB  H1? Co pB  H1?` }U H  0޽h ? 333gggy___PPT10Y+D=' = @B + Z Rw(    3 r@Agֳgֳ ?     C x$Fgֳgֳ ?J;K  & @   TdMgֳgֳ? A K  64K 512P8ckc  pB  H1?$ } $ H  0޽h ? 333gggy___PPT10Y+D=' = @B + [ S }(    3 rDlgֳgֳ ?s`  & @  Tgֳgֳ?y/ 3 4G 512L(ckc  pB  H1?Y Y  T(gֳgֳ?a   M~ ~b    TTgֳgֳ?"  v4M 512@Pckc  pB  H1? R    Tgֳgֳ?( f  222 29RPckck  pB   H1? 0 H  0޽h ? 333gggy___PPT10Y+D=' = @B +C \ jb0S(    C xgֳgֳ ?@ .'  & @   Tgֳgֳ?0   252 212Pckck  pB  H1?     Ngֳgֳ?   u = 240 = !< ckc  NF c9  ,  xB B H1?c9xB  H1?lH  0޽h ? 333gggy___PPT10Y+D=' = @B +  PSP(  x  c $     s *hS]<   & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +]  `S,,(  rF bf  bfl  <1?jd  TSgֳgֳ?O# a11 bits 11 bits 10 bitsb  xB  H1?f xB  H1? f 3  TSgֳgֳ? ISegment Number Page Number Displacement Base of Segment Table.0(Jb J N 3  3JN 0   0l   <1?/xB   H1? 0 l   <1?(/~B   N1?33&~B  N1?*  TSgֳgֳ?t K0 1b    TSgֳgֳ?b N2047xb    T|Sgֳgֳ?kB VSEGMENT TABLEb     BAC`DEF1?@@_ @   T|Sgֳgֳ?z  bBase Address of Page Tableb     BAC`DEF1?@@_ @  M e N c    c  N c    c  JN c   c l  <1?j xB  H1?cq ql  <1?j   ~B  N1?  ~B  N1?gg   TIgֳgֳ?{8  K0 1b    TIgֳgֳ?,^ 9  N2047xb    TIgֳgֳ?  S PAGE TABLE b  JN  \ T     \ T l ! <1? \ T xB " H1?  l # <1? k ~B $ N1?#U # ~B % N1? X  & T@gֳgֳ?A  YBase + 0 Base + 1b   ' TAgֳgֳ?  U Base + 1023 x b   ( T Jgֳgֳ?c X W XPAGE (in Memory)b   ) T[gֳgֳ?    \Base Address of Pageb   *  BC DEF1?  G @!  + TBgֳgֳ?Sf [Address within Pageb   , T(ngֳgֳ??y_ eTwo-level Address mappingd  H  0޽h ? 333gggy___PPT10Y+D=' = @B +a ^ S(    3 rgֳgֳ ?4  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +5 _ \TS(    3 r,gֳgֳ ?     C x0gֳgֳ ?7<  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +5 ` \TS(    3 r«gֳgֳ ?     C x ȫgֳgֳ ?@d'  & @H  0޽h ? 333gggy___PPT10Y+D=' = @B + a S^(    3 rgֳgֳ ?     C xPgֳgֳ ?}  & @jB @ B1?F `; H  0޽h ? 333gggy___PPT10Y+D=' = @B +b T99O(  F s   @I  NA [??zv X [$00  NA \??f X \$00l  <1?7  T4gֳgֳ?sti aVirtual page numberFb    T4gֳgֳ? 1 X Page table F b     BC~DE F1?}}@s rB  B B1?JJf2   61? 7 Uf2   61?  f2   61? : Xf2   61?  f2  61? = [f2  61? ; f2  61? I; gf2  61? ; f2  61? M ; k f2  61? ; f2  61? P ; n f2  61? ; f2  61? S ; q f2  61? ; f2  61? \ ; z f2  61? ; f2  61? Y ; w   NA ]??BX X ]$00N #    #  f2  61?  `  0?z . f2  61?#  xB   H1? v 0 xB ! H1?v 0 x " H1))? $ f # 61?" e f $ 61? D  % T4gֳgֳ?g M'  V Disk storage b  rB & B1? DrB ' B1? JJrB ( B1? TrB ) B1? JrB * B1? OrB + B1?7 rB , B1?9 WrB - B1?8 OrB . B1?1 EV rB / B1?2  rB 0 B1?; Rn rB 1 B1??  rB 2 B1?, k  rB 3 B1?+ R rB 4 B1?. j rB 5 B1?5   rB 6 B1?. g  7 T@4gֳgֳ?Z YPhysical memoryb   8 T4gֳgֳ?9   MTLBb  ( 9 N4gֳgֳ?` ZThe TLB acts as a cache on the page table for the entries that map to physical pages only [[g [ H  0޽h ? 333gggy___PPT10Y+D=' = @B + c " T(   0 TA ^? ? h ^$00  4  TH/gֳgֳ?V s'Some typical values for a TLB might be:((d (   C xH/1))? ~U _Miss penaly some time may be as high as upto 100 cycles. TLB size can be as long as 16 entries.` `a@    4 H  0޽h ? 333gggy___PPT10Y+D=' = @B +  @TV(  ~  s *$/P`  /   s *PMh& / & @H  0޽h ? 333gggy___PPT10Y+D=' = @B +Zd yPT++(  F Fi   F N } B  } Bl  <1?} B  TVgֳgֳ?K_  R TLB access b  N A,   A, lB  <1?A,   T`gֳgֳ?  b PTLB hit? b  rB   B1? >    Nkgֳgֳ?8i  WVirtual addressb  rB   B1? S *lB   <1? Ln   Ttgֳgֳ? @T NWrite?b     BCDE F1?@  N y   y l  <1?y   T0~gֳgֳ?{  gTry to read data from cachePb  N Q   Q l  <1?h   Tgֳgֳ?Q{  \Check protectionPb     BCDE F1?@     BCDE F1?@`N \    \  l  <1? I <  Tgֳgֳ?\   dWrite data into cache, update the dirty bit, and Put the data and the address into the write bufferePeb e rB  B1?  N K %   K % lB  <1?K %   T̜gֳgֳ? b  R Cache hit? b  rB  B1?  l  <1?F     Tgֳgֳ?F   XCache miss stallb  rB !B B1?Z =Z  "  BCFDE F1?E@ Z  # T8gֳgֳ? m  KYesb   $ Tgֳgֳ? [% # KYesb   % T,àgֳgֳ?9 KYesb   & T̠gֳgֳ?   JNob   ' TĠgֳgֳ? V JNob  rB (B B1?5 ) T͠gֳgֳ?g ^TLB miss exceptionPb   * Tgֳgֳ?   JNob  0 + Tgֳgֳ?  FProcessing a read or a write through the DECStation 3100 TLB and cacheGGf&)    H  0޽h ? 333gggy___PPT10Y+D=' = @B +(e ,'$'pT<< &(       `1))? J"F poq    opq AN )y?   )y?l   <1?-y9o   Tdgֳgֳ?R}  pid ip iw\bbjbjN       xB   H1?)=xB   H1?$ +$ ?   Tgֳgֳ?o / WVirtual addressb  N ;   ;N      l   <1?    T$gֳgֳ?Hs  X TLB Page map P b  ~B   N1? ~B   N1?& &"N h ;   h ;    BCDEF1? @h ;xB   H1?h `:`xB   H1?i