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' ! ,YkG= ;$&?mt<=?@CDEFG JKLMNOPQRST&UVWX&YZ[\&]^_` abcdefghijklmnopor$3x!tV$dir$fL4³@1ii"$.W DCb!k'V"$z*<ڊ7ΫCD ("${}f5@2$ʓB(Data-path control unit design Pipeline stalls on cache misses??b  ? 8!Actions Needed on an I-Cache Miss"P"` " 1. Compute the value of PC-4. 2. Instruct the main memory to perform a read and wait for the memory to complete its access. 3. Write the cache entry, putting the data from memory in the data portion of the entry, writing the upper bits of the address (from the ALU) into the tag field, and turning the valid bit on. 4. Restart the instruction execution at the first step, which will re-fetch the instruction, this time finding it in the cache.(`b  9A Case Study: DEC Station 3100P`  Separate I-Cache and D-Cache  Write-through policy One-word-line simplifies write-miss handlingaab a :How to Handle Read/Write`  Write Write-through: for both write hit/miss 1. Index the cache using bits 15-2 of the address. 2. Write both the tag portion (using bits 31 - 16 of the address) and the data portion with the word. 3. Also write the word to main memory using the entire address. D bb`  ;<Performance Penalty due to Write-Through on DEC Station 3100(=P,`b = CPI without cache misses: 1.2 (gcc), but with each write takes 10 cycles: CPI becomes 2.3 (gcc) Note: in gcc, 11% of instructions are stores, each takes 10 cycles Solution: write buffers (in DEC Station 3100: size=4)R`D6abbubZ  9     m <  =Combined I-Cache/D-Cache?2 b`b  ]Hit ratio: Combined may be better: In DECStation 3100: 4.8% vs 5.4% Bandwidth considerations4#"^b@'       >  The primary method of achieving higher memory bandwidth is to increase the physical or logical width of the memory system. In this figure there are two ways in which the memory bandwidth is improved. The simplest design, (a), uses a memory where all components are one word wide; (b) shows a wider memory, bus, and cache while (c) shows a narrow bus and cache with an interleaved memory.8byb b  'Review: Major Components of a Computer ]% Processor-Memory Performance Gap 6"The  Memory Wall )Logic vs DRAM speed gap continues to grow**"`&(Memory Performance Impact on PerformanceSuppose a processor executes at ideal CPI = 1.1 50% arith/logic, 30% ld/st, 20% control and that 10% of data memory operations miss with a 50 cycle miss penaltyP!9{9{,6a'The Memory Hierarchy GoalFact: Large memories are slow and fast memories are small How do we create a memory that gives the illusion of being large, cheap and fast (most of the time)? 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TDatapath d   <8c?`` \    Z5xaxa1?O$  KSecondary Memory (Disk)   <8c? f ,$D0   Zxaxa1?G,$0 DOn-Chip Components^B  6o?P ^B  6o? M d  <8c?J aA   ZZxaxa1? R  SRegFilex  PA8c?10% P0 x  PA8c?10%p   Z xaxa1?` f  JMain Memory (DRAM)   `Zp xaxa1?r U  B Data Cache  x  PA8c?10% P    `Zxaxa1?d  ] Instr Cache  x  PA8c?10% 0  @ T1?   <ITLB @ T1? @  <DTLB  B6'Ԕ?p` ,$D0 @ B81?4,$0 UeDRAM6'  Z" 8c 8c1?   "Speed (%cycles):  s 1 s 10 s 100 s 1,000 s8hU#V  Z( 8c 8c1? E jSize (bytes): 100 s K s 10K s M s G s to T sLqU  5'G1  TP0 8c 8c1?0 k Cost: highest lowest&lU]   Z4 8c 8c1 ? H 1By taking advantage of the principle of locality Can present the user with as much memory as is available in the cheapest technology at the speed offered by the fastest technologyH1 qK lK18c8XH  0޽h ?   ___PPT10 .+4D ' = @B D ' = @BA?%,( < +O%,( < +D ' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<* %(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(|D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%('D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+p+0+  ++0+ +Y! L0  ? (  d  <1?    `$Mxaxa1 ?P`   dR  <1? XB  0D1? ` #  <LO1? D ,$0 5Increasing distance from the processor in access time26*  <U1?P `  7L1$XB   0D1?@ XB   0D1? 0    <Y1?YP ` @ 7L2$   <]1?9 @@  A Main Memory     <a1?y P`  GSecondary MemoryB  6D1? ,$D0  H1?   = Processor B  <D1?Y Y ,$@0  <1? @p,$0 _+(Relative) size of the memory at each level,,z @``   @ ,$D0fB  6D1?@@`   <p1?@`  &Inclusive what is in L1$ is a subset of what is in L2$ is a subset of what is in MM that is a subset of is in SM&s j8  ) I  )  I lB  <D1? ) lB  <DjJ? i )lB  <DԔ?  I lB  <DjJ? I l  8-  8 - ,$D0  N 1? 8"  ^4-8 bytes (word)2   Bt 1? yM  ? 1 to 4 blocks  N1? Y -  o!1,024+ bytes (disk sector = page)2"  B1? m `8-32 bytes (block)2 H  0޽h ? U>=UU(  ___PPT10 +elD( ' = @B D ' = @BA?%,( < +O%,( < +D' =%(Du' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =%(Du' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(+p+0+ ++0+ + L0 z@(    C x4' 8c 8c1 ?R+     C xN 8c 8c1 ? 0 *   t  ZX( 8c 8c1 ?` ,$0 Main Memory uses DRAM for size (density) High density (1 transistor cells), low power, cheap, slow Dynamic: needs to be  refreshed regularly (~ every 8 ms) 1% to 2% of the active cycles of the DRAM Addresses divided into 2 halves (row and column) RAS or Row Access Strobe triggering row decoder CAS or Column Access Strobe triggering column selector)u*1gu*1              d  <1?^B  6Do?ppXB @ 0D1? ^B  6Do?XB  @ 0D1?``^B   6Do?  XB  @ 0D1?`P   <l81?P < Dout[15-0]    <<1?l @ SRAM 2M x 16    <TA1?` w ; Din[15-0]   <D1?0  9Address  <G1? 0  = Chip select   <pK1?p  ? Output enable  <1? t > Write enable ^B  6D1?00^B  6D1?pp^B  6D1?  <l1?P 416  <T 1?PP 416  <x 1?P 421H  0޽h ? X(=^___PPT10+PQFDO' = @B D ' = @BA?%,( < +O%,( < +DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*%(+8+0+ + L0 `D$(  r  S P`   r  S @P`  H  0޽h ? X(=^___PPT10i.8v+D=' = @B +" L0 ?++I(    S ~! 8c 8c1 ?_   ~  VA1?20% |   Z# 8c 8c1?pH  JR o w D e c o d e rUd  <8c?X XB  08c?`h( `XB  08c?Ph( PXB  0p?@p @XB   08c?0h( 0XB   08c? h( XB   08c?h( XB   08c? h( XB   08c? h( dB  <Ԕ?    ZD. 8c 8c1? (  A row address U d  <8c? ( jB  BԔ? @@X  Z3 8c 8c1?p # Fdata bit or wordUXB  08c?@@ XB  08c?00 XB  08c?   XB  08c? XB  08c?  XB  08c?  XB  08c?     `$9 8c 8c 1? FRAM Cell ArrayUz  x     x ,$D0fB  61? l    Z> 8c 8c1?( x Eword (row) lineUz     ,$D0fB  61? <    ZC 8c 8c1? s Fbit (data) linesUz   !  ,$D0fB " 61?  D # T@Gxaxa1? r@Each intersection represents a 6-T SRAM cell or a 1-T DRAM cellAAXB $ 0o?  %  `L 8c 8c1? (  V Column Selector & I/O Circuits!! &  `O 8c 8c1?@ X  Bcolumn addressjB '@ BԔ? 0  ( TPxaxa1? ` 0 ,$D0 mOne memory row holds a block of data, so the column address selects the requested bit or word from that blockNnRXB ) 0o? 0 XB * 0p? 0 XB + 0jJ? 0 H  0޽h ? X(=^ w ___PPT10W +5D ' = @B D ' = @BA?%,( < +O%,( < +D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*!%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(D4' =%(D' =%(D' =4@BBBB%(D' =1:Bvisible*o3>+B#style.visibility<*%(DA' =%(D' =%(D' =A@BBBB0B%(D' =1:Bvisible*o3>+B#style.visibility<*(%(+8+0+( +), L0 8+0+?XX*(  F %Q B   0\\   VA1?20%IQ `B  08c?- `B  08c?-r r`B  0p?5b b`B  08c?-R R`B  08c?-B B`B   08c?-2 2 `B   08c?-" " `B   08c?-  `B   08c?: `B   08c?: `B  08c?: `B  08c?: `B  08c?: `B  08c?  : `B  08c?  : `B  0p?  B `B  0Do?%B    Zx  8c 8c1?  `  <data bit   Z 8c 8c1?0 S >data bit U   C xh 8c 8c1 ?l`     Z 8c 8c1?   JR o w D e c o d e rUd  <8c?* dB  <Ԕ? ee   Z 8c 8c1? e  A row address U   Z@ 8c 8c1?b   X Column Selector & I/O Circuits!U!d  <8c?:    Zd 8c 8c1? ]X  Dcolumn addressUdB @ <1? 0   Z  8c 8c1?0@  >data bit U  " Z( 8c 8c1?p#  Eword (row) lineU^B # 61?  $ Z, 8c 8c1? @c Fbit (data) linesU % T0xaxa1?! _-Each intersection represents a 1-T DRAM cell.. &  d2 8c 8c1 ?    pr ' H1? @  9. . .F %Q B  1 `P|  2 VA1?20%IQ `B 3 08c?- `B 4 08c?-r r`B 5 0p?5b b`B 6 08c?-R R`B 7 08c?-B B`B 8 08c?-2 2 `B 9 08c?-" " `B : 08c?-  `B ; 08c?: `B < 08c?: `B = 08c?: `B > 08c?: `B ? 08c?: `B @ 08c?  : `B A 08c?  : `B B 0p?  B `B C 0Do?%B  F %Q B  D %Q B  E VA1?20%IQ `B F 08c?- `B G 08c?-r r`B H 0p?5b b`B I 08c?-R R`B J 08c?-B B`B K 08c?-2 2 `B L 08c?-" " `B M 08c?-  `B N 08c?: `B O 08c?: `B P 08c?: `B Q 08c?: `B R 08c?: `B S 08c?  : `B T 08c?  : `B U 0p?  B `B V 0Do?%B   W  `\L 8c 8c 1?  FRAM Cell ArrayUjB X@ BԔ?  ^B ! 61? & H  0޽h ? X(=^y___PPT10Y+D=' = @B +e9 L0 33+3@jj2(    C x \ 8c 8c1 ?3      C xD] 8c 8c1 ?p   l   j ,$D0`B  08c?hHh`B  08c?(H(`B  08c?Xp `B  08c?X`0`B  08c?hh`B   08c?((`B   08c?p8 `B   08c?`80`B   08c?8 h h`B   08c?8 ( (  Zaxaxa1?hJ: ? Row Address fB  68c? P`B  08c?H H `B  08c?P X `B  08c?h x `B  08c? @ `B  08c?