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Also, if alternatively use 2 blocks which mapped into the same cache block frame:  trash may happen. f  2h bSbbb@M   e  k  Note`  Main memory size: Smain (blocks) Cache memory Size: Scache (blocks) Let P = Since P >>1, average search length is much greater than 1. Set-associativity provides a trade-off between concurrency in search average search/access time per block#t /;`h!`hY`/`;`Z     ]   Y     "Important Factors in Cache Design#P#` # [Address partitioning strategy (3-dimention freedom) Total cache size/memory size Work load4 '\b  \  Address Partitioning`  Byte addressing mode Cache memory size data part = NKL (bytes) Directory size (per entry) M - log2N - log2L Reduce clustering (randomize accesses)+  'dbjbj)b   Note: The exists a knee`    & the data are sketchy and highly dependent on the method of gathering... & designer must make critical choices using a combination of  hunches, skills, and experience as supplement&  a strong intuitive feeling concerning a future event or result. I  2 `ds`dd`d/`   Basic Principle`  Typical workload study + intelligent estimate of others Good Engineering: small degree over-design  30% rule Each doubling of the cache size reduces misses by 30% by A. Smith It is a rough estimate only2n^n`^`   Cache Design Process`   Typical , not  Standard  Sensitive to: Price-performance -- Technology main M access time cache access chip density bus speed on-chip cachen* E*`bbE b    Cache Design Process`  (Step 1 : Choose Size fix K, L, varying N$)`b ) 1Step 2 : Choose L fix NKL = size and K, varying L$2` b 2 1Step 2 : Choose K fix NKL = size and L, varying K$2` b 2  N: Set number`  ^Cache directory# = N K Cache size = N K L Constraints in selection of N: (page size)_ _` _ K: Associativity`&    QBigger miss ratio Smaller is better in: faster Cheaper 4 ~ 8 get best miss ratioH))``` R  L : Line Size`  Atomic unit of transmission Miss ratio Smaller Larger average delay Less traffic Larger average hardware cost for associative search Larger possibility of  Line crossers Workload dependent 16 ~ 128 byteH/x|x!x/`|`!`  Cache Replacement Policy`  FIFO (first-in-first-out) LRU (least-recently used) OPT (furthest-future used) do not retain lines that have next occurrence in the most distant future Note: LRU performance is close to OPT for frequently encountered program structures.@P ``R`  Program Structure`   for i = 1 to n for j = 1 to n endfor endfor last-in-first-out feature makes the recent past likes the near future4  [ ```` `` ```` `` ````H`L 6    I U,)Why LRU and OPT are Close to Each Other?*P*` * LRU : look only at past OPT : look only at future But, recent past nearest future Why? (Consider nested loops)l\  2   2 b```  Problem with LRU`  Not good in mimic sequential/cyclic Example ABCDEF ABC& & ABC& & With a set size of 3N,x x ,``` Y Sequential Access`  Empirical Data`  NOPT can gain about 10% ~ 30% improvement over LRU (in terms of miss reduction)O O` O   A Comparison `  OPT has two candidates for replacement LRU only has one the least-recently used -- it never replaces the most recently referenced deadline in LRUZ Z+``Z`  %#+Performance Evaluation Methods for Workload,P,` , (Analytical modeling Simulation Measuring))` ) &$Cache Analysis Methods`  tHardware monitoring fast and accurate not fast enough (for high-performance machines) cost flexibility/repeatability2a`a` u '%Cache Analysis Methods`  Address traces and machine simulator slow accuracy/fidelity cost advantage flexibility/repeatability OS/other impacts - how to put them in?2%g%`g`  (&"Trace Driven Simulation for Cache#P#` # Workload dependence difficulty in characterizing the load no general accepted model Effectiveness possible simulation for many parameters repeatabilityd@6`@``6`  )'Problem in Address Traces`  Representative of the actual workload (hard) only cover milliseconds of real workload diversity of user programs Initialization transient use long enough traces to absorb the impact Inability to properly model multiprocessor effects~-D,3-`D``,`3`  *( An Example `  Assume a two-way associative cache with 256 sets Scache = 2 x 256 lines Assume that the difficulties of count or not count the initialization causes 512 more misses than actually required Assume a trace of length 100,000 with hit rate 0.99 than 1000 misses is generated the 512 makes big difference!! If want 512 miss count less than 5% then total misses = 512/5% = 10,240 miss thus with hit = 0.99 required trace length > 1,024,000!v#n* nNn) n"nV n%nd nb&6   +) o One may not know the cache parameters before hand What to do?? Make it longer than minimum acceptable length!p f 2f ffff o ,* S100,000? too small (10 ~ 100) x 106 OK? 1000 x 106 or more being used now ..     $`h`h` T /-./0123456 7 8 9 : ;<=>?@BCDEFKLM N!O"P#Q$R%>,  0` @EoOV` @Eff؂o` MMMwww` 33f3Ƨgzf` 3ffE` JH3f̙ff` 33̙fRP` =bf>?" dd@(? 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