LORAN-C Timing Receiver
16 January 1993

This file contains revisions to the circuit board as the result of
ECOs.

The input terminals A1.9 and A1.10 of A1C are reversed. Isolate these
pins and connect A1.9 to any pin on net {D5.2 R11.1 R12.2} and A1.10
to any pin on net {C18.1 C17.1 R5.2 R7.2 D4.1 A1.3 T1.3 A1.5}.

Pins U7.7 and U10.7 (DAC output amp reference voltage) should be
connected to pins U7.6 and U10.6 (DAC reference voltage), respectively.
No traces need to be cut.

Pins S1.14, S2.14 and S3.14 are switched with pins S1.3, S2.3 and S3.3,
respectively. All 6 pins should be isolated by cutting the traces near
the pins, making sure not to break continuity with other pins on the
same net. Then, pins S1.3, S1.15, S2.3, S2.15, S3.3 and S3.15 should be
connected to the AGND net and pins S1.14, S2.14 and S3.14 should be
connected to the VCC net.

There is a new net connecting the analog ground of the VCO DAC through
the 25-pin cable to the VCO analog ground. It removes a ground loop in
the original design. Cut the trace to isolate U7.4 and U7.5 from the
remainder of the AGND net and connect a wire between J2.9 and U7.5.
There should already be a trace between U7.4 and U7.5.

Pin U5.10 should disconnected from the ENG net and grounded instead to
the GND net. This change is optional; it is not used in the pal
equations and does not affect operation.