ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #9 - due Friday, 19 April 2002

1. Submit a set of corrected L-Edit plots of your CMOS circuit project.

Include the following:

1. A composite (all layer) plot of your circuit (use translucent fill patterns so the reader can evaluate details)
2. Individual separate black/white (no color or fill) plots for each mask level:
a. p diffusion (pMOS S/D and p-well/tub for nMOS)
b. n diffusion (nMOS S/D )
c. gate oxide (for p and n) include cuts and substrate
d. contact cuts and substrate
e. metalization (gate, S, D) - image reversed

We will use a lambda of 7.5 microns. That means that the transistor gates will have Z = 150 microns and L = 30 microns.

Include alignment marks on each level and body contacts.
Please provide the circuit schematic, logic gate diagram, Boolean expression and the truth table so the type of circuit is clear.

2. (a) Calculate the junction depth x_j and the total amount of dopant (dose) introduced into an n-type substrate with a bulk concentration C_B of 1 x 10¹⁵ cm^-3 , after boron predisposition at 975 °C for 60 minutes. (b) Calculate the new junction depth after a drive-in diffusion at 1100 °C for 4.5 hours.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
due date, assignment number and the course number.