ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #8 - due Wednesday, 10 April 2002

1. Submit a full L-Edit plot of your CMOS logic circuit project.
Plot a composite with all 5 layers (p diffusion, n diffusion, gate oxide, contact cuts and metal) on one page with easy-to-read fill patterns, and also separate plots of

one mask layer per page (use solid black fill) for each layer.
Indicate overlaps and use lambda = 7.5 microns. Indicate distances and include a legend of layer fill patterns.
For full credit, on a separate page, include the circuit schematic, logic gate diagram, Boolean expression and the truth table.
This assignment will be graded on the correct features, not so much on the efficiency of the lay out. Optimizing can be performed later.

2. Calculate the oxide thickness after 2 hours at 950 °C of dry oxidation for (100) Silicon. This will be similar to our gate oxide.

Perform an analytical calculation using appropriate values for the linear and parabolic rate constants at this temperature.

Compare your analytical value with the value from a graph such as Fig. 3.6 in Jaeger.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
the due date, assignment number and the course number.