ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #7 - due Wednesday, 27 March 2002

1. Submit a first draft L-Edit plot of your CMOS logic circuit project.
Plot a composite with all 5 layers (p diffusion, n diffusion, gate oxide, contact cuts and metal) on one page with easy-to-read fill patterns
Indicate overlaps and use lambda = 7.5 microns. Indicate distances and include a legend of layer fill patterns.
For full credit, on a separate page, include the circuit schematic, logic gate diagram, Boolean expression and the truth table.
Hint: this assignment will be graded on including the correct features, not on how efficiently it was laid out. Optimizing the layout will be performed later.

2. Following the example with silicon performed in class, calculate the oxide thickness after the third step of: 1 hour dray oxidation at 1100 C.

To obtain the initial time t, use the initial conditions obtained in class, that the staring thickness was 0.494 mm.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
the due date, assignment number and the course number.