ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #6 - due Monday, 18 March 2002

1. Submit an L-Edit plot of a CMOS inverter. Show and label input, output, V_DD and ground. Use the ELEG650 design rules for L, W and overlaps with size parameter l = 7.5 microns. Indicate distances and include a legend of layer fill patterns.

2. Submit a transistor circuit diagram (transistor symbols, not a graphics layout plot) of your CMOS circuit project. Your project circuit may use NANDs, NORs and Inverters. For ease of fabrication, keep the total number of transistors to below about 20, and use 3 or less input and output lines, plus 2 more for V_DD and ground. Feel free to depart from your previous submission.
Re-include the Boolean expression and Truth table (to make it easier for the grader to follow). Hint: now is the time for any modifications to your previous design.

3. For a CMOS inverter circuit biased in “region B” of the input - output characteristic, with V_Tn < V_in < V_DD/2, calculate a numerical value for the drain current, I_DSn. . Use the following device parameters: mobilities m_n = 500 cm²/V-s, and m_p = 200 cm²/V-s; d_ox = 10 nm; nMOS sizing: W_g = 5 um and L_g = 1 um; V_Tn = -V_Tp = +1 Volt. Assume that the pMOS device is sized such that the inverter ratio, b_R = 1, and that V_DD = 5 Volt..

4. Carry out the steps to determine dV_out/dV_in = -1 that were needed to obtain a numerical value to the input noise margin parameter, V_ILmax. Show the numerical values.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
the due date, assignment number and the course number.