1. Using L-Edit, design the mask layout pattern for an nMOS transistor.
Follow ELEG 450/650 course design rules for size, spacing and overlap. Label your layers:
diffusion, gate oxide, contact cuts, and metal (gate, source/drain).
Indicate the scale either by plotting a ruler, or by manual marking with a pen. Did you include all the dimensions so that a fab-house would be able to make your transistor? Use whichever fill patterns are convenient to view, plot, and for you to remember. Submit a top-view composite plot containing all 4 layers, with lables and scale.
Use an appropriate magnification so that your plot reasonably fills the page.

2. Submit a descriptive plan for your course project. This must include some CMOS circuitry, but may also include MEMS structures if you wish. Include a circuit schematic and a logic diagram with a logic symbol truth table. The MEMS structures can be formed using n-type substrate regions surrounded by p-type diffused regions. The n-type regions will remain free-standing after the p-type diffused regions are preferentially etched away during fabrication. Note: you will have an opportunity to edit and modify your design project during the semester.

See Graphics Layout Editors Site website for printing hints.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/courses/ELEG650S02.htm. 

Note: On each homework and report submission, give your name,
the due date, assignment number and the course.