ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #3 - due Friday, 22 February 2002

1. Using L-Edit, plot 3 rectangles of different layers selected from the Layer Palette window. Use any convenient size rectangle, but 50 microns x 100 microns is practical.
In a legend region alongside your rectangles, use the Port Tool to label and identify the fill patterns and/or colors that you used for each layer. Label the 3 layers as: Diffusion; gate oxide; and metal. This structure will be similar to our MOS transistor.

See Graphics Layout Editors Site website for printing hints.

2. An Au gate MOS capacitor is fabricated on an n-Si substrate with N_d = 10 ¹⁵ cm^-3 . The thickness of the gate oxide is 120 nm, and the charge density at the Si-SiO₂ interface is 3 x 10 ¹¹ charges cm^-2. Calculate: (a) the flat band voltage; (b) the threshold voltage; and (c) sketch the energy band diagram under thermal equilibrium at the onset of strong inversion.

3. An Al gate enhancement type n-channel Si MOSFET has a substrate concentration N_a = 6 x 10 ¹⁵ cm^-3 and on oxide thickness of 100 nm. The SiO₂ has 10 ¹⁰ charges cm^-2. (a) Determine the threshold voltage. (b) When operated in the linear region with V_D = 0.5 V, calculate the gate voltage V_GS to obtain a drain current of 2 mA. Assume L = 10 mm, mobility m_n = 500 cm²/V-s, and W = 100 L.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: For proper credit, on each homework and report submission, give your name,
the due date, assignment number and the course.