ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #10 - due Friday, 26 April 2002

1. Submit a set of corrected L-Edit plots of your CMOS circuit project.

Include the following:

1. A composite (all layer) plot of your circuit (use translucent fill patterns so the reader can evaluate details)
2. Individual separate black/white (no color or fill) plots for each mask level:
a. p diffusion (pMOS S/D and p-well/tub for nMOS)
b. n diffusion (nMOS S/D )
c. gate oxide (for p and n) include cuts and substrate
d. contact cuts and substrate
e. metalization (gate, S, D) - image reversed

Use lambda = 7.5 microns, so the transistor active channels (same for p and n) will have Z = 150 microns and L = 30 microns.

Include alignment marks on each mask level and body contacts on the substrate and on each well.

It is heartily suggested to join all p wells.

Use a single pad for each signal and power contact- roughly 200 mm x 200 mm. Note that ELEG 450/650 uses no poly and only 1 metal level.

If you need to cross signal lines, use diffusion as an underpass.
For full credit include the circuit schematic, logic gate diagram, Boolean expression and the truth table.

2. Problem 4.8 (a), (b), (a) in Jaeger, with reference to figure 4.15 regarding resistor ends. For part (c), assume that the base diffusion has a Gaussian profile.

3. Problem 5.1 (a), (b), (a) in Jaeger. Assume that ion implantation through the oxide has the same range and straggle as through Si, so you may use figure 5.3.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/. 

Note: On each homework and report submission, give your name,
due date, assignment number and the course number.