ELEG 450/650        Spring 2002           Schedule (rev. 6 May 2002)                J. Kolodzey

Week     Date        Lecture                                        Laboratory                                      Assignment

 

1              2/4           Handouts                                    L-Edit Practice                                Read Safety Manual

                                Course overview                                                                                  Read Lab Guidelines.

                                Lab Safety                                                                                             Read Jaeger pp. 1-14

 

2              2/11         Lab Safety                                   L-Edit Practice                                nMOS Transistor Layout

                                MOSFET operation                                                                             Read Jaeger pp. 17-40

                                L-Edit overview                                                                                    Read Uyemura pp. 1.1-1.22

                                Process overview                                                                                 Read H&H pp. 514-530

 

3              2/18         Inverters                                      Field oxidation                                Jaeger pp. 43- 64. Choose circuit

                                Photolithography                                                                                 project.  Read H&H, pp. 542-552.

                                Digital Circuits

                                Metal Gate Process

 

4              2/25         Device sizing.                             p-Diffusion lithography                Jaeger pp. 67- 87.

                                Layout criteria                            p-Diffusion window etch              H&H pp. 530-535.  Circuit

                                Design rules. logic                     for pMOS S/D; p-tub                     project description due. 

                                design, device layout                                                                         

                                                                                     

 

5              3/4           Inverters                                      Boron diffusion                              Circuit schematic diagram due.

                                Digital Circuits                                                                                      Test discrete circuit version. 

                                Noise margins                                                                                       Jaeger pp. 87 - 102

                                                                                     

6              3/11         Mask design                               2nd Field oxidation                          Circuit mask set due.

                                Process testing                                                                                     Read Jaeger  Chapter 5.

                                Threshold control                                                                                MOS layout design rules Quiz Wednesday

                                Etching

 

7              3/18         Circuit layout                              n diffusion lithography                 Review Jaeger  Chapter 2

                                                                                      n-Diffusion window etch              Build discrete version of circuit

 

8              3/25         Atomic Diffusion                       Phosphorus diffusion                   H&H pp. 536-541

                                                                                                                                                Read Jaeger  pp. 201- 228; 277 - 279.

                                                                                                                                                Test discrete version of circuit

                                                                                     

9              4/8           Diffusion                                     Gate oxide lithography                  Jaeger  pp. 183-195, 235-243

                                                                                      Gate oxide etch                               Circuit project mask set due

                                                                                      Gate oxidation                                 H&H pp. 542-552

                                                                                     

10            4/15         Oxidation                                     Contact cut lithography                Revised mask due.

                                                                                      Contact cut etch                             Read Jaeger Chap 3; pp. 151-173.

                                                                                                                                                Hour Quiz April 17

                                                                                                                                               

11            4/22         MEMS design                            metal liftoff lithography                Read Jaeger Chap 11; pp. 194 - 198

                                                                                                                                                Final corrected mask due

                                                                                       

12            4/29         SUPREM simulations                metal evap. and liftoff                    Read Jaeger Chap. 6

                                FET Device testing                    Circuit Testing I                             H&H pp. 535-536, 541-542

 

13            5/6           Circuit testing                             Emulsion mask making                  Read Jaeger Chap. 9

                                Circuit delay times                     Demo circuit to TA                       

                                                                                                                                               

 

14            5/13         Circuit power dissip.                  Ferrox mask making/demo            Comprehensive Final Report

                                Vacuum systems.                       Prepare final reports                      due Thursday, 23 May, 4:30 pm

                                                                                                                                                Final Exam: 5/22, 10:30 - 12:30