1.
Submit a set of corrected L-Edit plots of your CMOS circuit
project.
Include the following:
1. A composite (all layer) plot of
your circuit
2. Individual separate black/white plots for each mask
level:
a. n diffusion (n-chan S/D and well/tub for p-chan)
b. p
diffusion (p-chan S/D )
c. gate oxide (for p and n) include cuts and
substrate
d. contact cuts and substrate
e. metallization (gate, S, D) -
image reversed
Note that future assignments will include a 40:1 scaled composite (all layer) plot of your
circuit die which
includes several (4-6) copies of your circuit, plus some
inverters
and individual n and p transistors
We will use a lambda of
6 microns. That means that the transistor gates will have Z =
120 microns and L = 24 microns (instead of 200/40) Please include the
circuit schematic. logic gate diagram, Boolean expression and the truth table.
This assignment should include 7 plots plus a schematic/logic diagram.
See Graphics Layout Editors Site website for printing hints.
Homework assignments will appear on the web at: http://www.ece.udel.edu/~kolodzey/.
Note:
On each homework and report submission, give your name,
the due
date, assignment number and the course.