1. Using L-Edit,
design the mask layout pattern for an nMOS
transistor.
Follow ELEG650 course design rules for size, spacing and
overlap. Label your layers:
diffusion, gate oxide, contact cuts, and metal
(gate, source/drain).
Indicate scale either by plotting a ruler, or by manual marking.
Did you include all the dimensions so that a fab-house would
be able to make your transistor?
Use whichever fill patterns
are convenient to view, plot, and to remember (just label them).
Submit a top-view composite plot containing all layers.
Use an appropriate magnification so that your plot reasonably fills the page.
2. Do Exercises 14-3 and 14-4 in Hamilton and Howard, p. 534.
Note that the 2 values for Vout given in the equations on p. 534 are for the
special case kD = kL, whereas Exc 14-4 is for the general case kD not equal to kL.
See Graphics Layout Editors Site website for printing hints.
Homework assignments will appear on the web at: http://www.ece.udel.edu/~kolodzey/.
Note:
On each homework and report submission, give your name,
the due
date, assignment number and the course.