ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #3 - due Friday, 23 February 2001

1. Using L-Edit, plot 3 rectangles of different layers selected from the Layer Palette window. Use any convenient size rectangle, but 50 microns x 100 microns is practical.
In a legend region alongside your rectangles, use the Port Tool to label and identify the fill patterns and/or colors that you used for each layer. Label the 3 layers as: Diffusion; gate oxide; and metal. This structure will be similar to our MOS transistor

See Graphics Layout Editors Site website for printing hints.

Homework assignments will appear on the web at:   http://www.ece.udel.edu/~kolodzey/

Note: On each homework and report submission, give your name,
the due date, assignment number and the course.