ELEG 450/650 Integrated Circuit Design and Fabrication
Homework #12 - due Monday, 7 May, 2001
1. Submit final corrected L-Edit plots of all 5 separate mask layers of
your circuit die. Your die includes several copies of your circuit
and substrate (body) and n-well contacts, discrete
transistors, and isolated inverters, for testing and diagnostics.
Make
sure the plotted figures are scaled 40:1 to the real silicon size.
In
addition, include: (a) composite plot showing all layers,
(b) full page
composite of just one circuit so that the TA and I may check dimensions more easily, and (c) logic diagram and truth table.
Correct any errors, but
do not make unnecessary changes.
Reminder: we have officially changed our value for lambda from 10 microns
and 7.5 microns
to 6 microns.
This means that the transistor gates will have Z = 120
microns and L = 24 microns (instead of 200/40 or 150/30)
For proper credit, include the course number, assignment number, and
due
date and your name on your submission.