Virtual Wires

To overcome I/O limitations and to satisfy connectivity and timing requirements, we developed a multiplexing scheme that we call virtual wires. As with Mahowald's [1] method of connecting neuron outputs to synapses, addresses are used rather than direct connections carrying spikes. In our scheme, the outputs of active neuromorphs and sensors (i.e., those that are currently producing a spike) cause the synapses that they connect with to become activated after a delay which is programmable for each connection. The number of connections (i.e., the fanout) is implementation dependent. In our present system (see photo below), each neuromorph may connect to sixteen synapses.

Virtual wires are formed using four circuits: 1) Row and Column Synapse Address Decoding, which selects a particular on-chip synapse. 2) State Machine, which determines sensor and neuromorph output states. 3) Connection List, which specifies the locations of synaptic connections, the axonal delay associated with each connection, and, optionally, a synaptic conductance. 4) Delayed Connection Memory, which holds particular synaptic activations for a future time.

The figure below illustrates a simplified single-domain system comprising four neuromorphic chips, each of which contain a number of neuromorphs. The outputs of the neuromorphs on each chip are sampled via a decoder-multiplexer, which decodes the neuromorph address (NA) supplied by the State Machine. Periodically, the State Machine reads the state of every neuromorph in its domain. When a neuromorph spikes, it is detected by the State Machine which then activates all of the synapses that connect to that particular neuromorph by using the information stored in the Connection List.

1. Mahowald, M.A. (1991) "Evolving Analog VLSI Neurons," in Single Neuron Computation, McKenna, T., Davis, J., and Zornetzer, S. F. (eds) Academic Press, Chap 15.

Simplified block diagram of Domain Board. The State Machine detects the occurrence of neuromorph spiking and makes the connections between it and its destination synapses by looking up the connections in the Connection List (CL). Those connections that have a non-zero axonal delay are temporarily stored in the Delayed Connection Memory (DCM) until their time has expired, after which they connect to their destination synapses. Afferent spikes generated by other Domain Boards enter through the Afferent Input FIFO (IF). All spikes occurring on a board and the time at which they occurred are stored in a Spike History FIFO (SH) which is read by a Sparc Station processor. Address Event (AE) (i.e., the neuromorph address, NA) data is used to directly drive external units such as actuators.

Definitions:

NI: Network Interface
IF: Input FIFO (First In First Out memory)
SH: Spike History Memory
CL: Connection List Memory
AE: Address Event
SO: Spike Output
CS: Clear Spike
NA: Neuromorph Address
SA: Synapse Address
RD: Row Synapse Address Decoder
CD: Column Synapse Address Decoder
SM: Spike Memory
A: Activate synapse
D: Axonal Delay
C: Synapse Conductance
S: Subsystem Address

Photo of Domain Board

The Domain Board is a six-layer VME compatible circuit board that provides connectivity and control signals for sixteen neuromorph chips. The circuitry on the left half of the board is primarily digital while the neuromorph chips are primarily analog. The digital circuitry handles the dynamic connections between neuromorphs, records spiking activity, generates switched capacitor clocks, provides for external afferent connections, and interfaces to a controlling computer through the VME bus. The board is currently used in both a SPARC based system and with a PC through a VME adapter.