Tutorial 1:
Go step by step on the following tutorial:
Introduction to VHDL Simulation
After you finished it, you have to modify the code to increment the output every N clock cycles where N is cycled between 1 and 2. So after the 1st clock cycle – the counter becomes to 1, after the 3rd clock cycle – it becomes 2, after the 4th clock cycle – it becomes 3, and so forth. Turn in listing of your code and waveform snapshot showing CLKIN, DOUT and COUNTER signals.
Tutorial 2:
To do this tutorial you have to update both .synopsys_vss.setup and synopsys_vhdl_setup.source files. Download them again from the downloads section and replace the old ones; or you can also find this files compressed in tutorial2.zip.
Turn-in assignment – (a) Explain differences between pre- and post- simulation results. Why are the results different? (b) Modify the code by adding a reset input signal to the watch entity. Rerun pre- and post- synthesis simulations using modified testbench that includes the reset signal (that will be provided). (Note: Your new entity should have the reset between clkin and dout). Why are the results identical?
Entity definition with reset:
entity watch
port(
clkin : in std_logic;
reset : in std_logic;
dout: out std_logic_vector (6 downto 0)
);
end watch;
Hint: in digital logic design, reset is usually applied upon startup to initialize all internal registers to a known value. Turn in listing of your code and waveform snapshot showing CLKIN, RESET, DOUT and COUNTER signals.
Tutorial 3:
You will be given TX-RX VHDL code that takes 7 bits of input from the PC (using parallel port cable and the XSPORT utility). The 0th input bit (or LSB) is the active low reset signal. The remaining 6 bits are serially transmitted over the gigabit link. On the receive side (RX code), the code takes 6 bits output from gigabit receiver and displays them on the 7-segment display.
Synthesize the code, generate the bit-file, program the board, and run the board with gigabit cables connected in loop-back mode (TX+ connected to RX+ and TX- connected to RX-). As shown below:
IMPORTANT NOTE: When using XSPORT - Never change D7 to "0". It will enable flash outputs that are physically connected to the serdes board causing a hardware damage.
7-segment display uses 4 bits as inputs; these bits are D2-D5 in XSPORT. The board should work as follows:
When you input “10000111” into XSPORT, the 7-segment display should show a “1”. When you input “10101001”, the display should show an “A”.
Turn-in assignment – use the gigabit scope to display the transmitted output for bit pattern “101100”. Print a time-domain waveform and an eye diagram. What is the rise-time and fall-time (10%-to-90%) of the gigabit output signal? Try a different bit pattern. Do different bit patterns change the eye-diagram? If they do, explain why you think this is happening.
Tutorial 4:
The VHDL TX-RX code from tutorial 3 is now supplanted with VHDL testbench and simulation models of gigabit transmitter and receiver chip.
Run pre-synthesis simulation that includes testbench, TX-RX code and gigabit transceiver model. Synthesize the TX-RX code. Run simulation that includes original testbench, original gigabit transceiver model and post-synthesis TX-RX code. Turn-in two waveforms showing pre- and post- synthesis simulation results.
Note: Tutorial 4 simulation files shouldn't be synthesized, those files are used for simulation only. You just have to synthesize tutorial 3 files (tutorial3.vhd TX.vhd and RX.vhd) and obtain a file named tutorial3_synthesis.vhd using ISE Xilinx as you did in tutorial 2.