CPEG 422/622 - COMPUTER SYSTEM DESIGN II - SYLLABUS

Meeting Information: Tue/Thu 11:00am – 12:15pm (046 Colburn Lab) 

Instructor Information: Prof. Fouad Kiamilev, 107 Evans Hall, x8969, kiamilev@udel.edu

Office Hours: Tue/Thu, 12:15pm - 1:15pm, 107 Evans Hall (or by appt.)

TA Information: Jirar Helou , 118 Evans, x3278, jirar@udel.edu

Office Hours: Tuesday 2pm- 4pm, 118 Evans Hall (or by appt.)

Project Assistant: Claudia Barrera , 112 Evans, x6361, cbarrera@udel.edu

Office Hours: Mon/Wed, 10am-12m, 112 Evans Hall (or by appt.)

Class Web-Site:         www.eecis.udel.edu/~cbarrera/cpeg422/

 Laboratory Information:

133 Evans Hall – 16 Sun Unix Workstations (Synopsys/Xilinx tools run on these machines)

132 Evans Hall – 26 XP/Linux Workstations (Hardware lab OR remote login to SUN in 133)

140 DuPont Hall – 24 XP Workstations (remote login to SUN in 133)

118 Evans Hall – TEKTRONIX Oscilloscope TDS7254B  (please make an appointment with Claudia Barrera (cbarrera@udel.edu ) to use the scope.

Textbook: Introductory VHDL: From Simulation to Synthesis, by Yalamanchili, Prentice Hall; ISBN: 0130809829 (1^st edition) OR ISBN: 0131457357 (2^nd edition).

Course Description:  Examines modern digital computer design methods using industry standard electronic CAD synthesis tools. Topics include hardware design using VHDL, logic synthesis tools, simulation methods for synthesis and efficient coding techniques for synthesis. Includes experimental laboratory work to design and evaluate FPGA-based digital computer hardware. Text chapters 1-8 will be covered in detail. Two projects will be given covering gigabit network interfaces and gigabit bit error rate testing. At the end of this course, you should be able to design, code, synthesize and test a complete digital design using VHDL simulation and synthesis tools and FPGA devices. This course uses industry-standard design tools and FPGA devices.

Collaboration: For projects, you will team in groups of 2. Homework and tests are to be completed individually.

Hardware: Each group will be issued an FPGA-based development board. These boards are susceptible to static damage and require using grounding strips. We will test each board at the time of issue; thereafter, it will be the responsibility of the team to take proper care of the board. While we will attempt to repair/replace non-functional boards, we only have a few spares.

Grading Policy:

Assignments & Projects are due at end of class period. Late submission automatically looses 50% of grade.