Principles of computer system design are studied emphasizing tradeoffs involving cost, performance, testability, reliability and manufacturability. Topics include timing analysis, component and subsystem interconnect, noise effects, debugging techniques, boundary scan testing and printed circuit layout. Laboratory work involves design and implementation of a computer subsystem.
Lecture: Mon/Wed/Fri 10:10am – 11:00am (140 DuPont Hall)
Lab: Tues 2:00pm – 5:00pm (140 DuPont Hall)
Instructor: Prof. Fouad Kiamilev, 107 Evans Hall, x8969, kiamilev _at_ udel.edu
Office Hours: Wed/Fri, 11am-12pm, 107 Evans Hall (or by appt.)
TA: Jason Blankenberg, 114 Evans, x1633, jblank _at_ udel.edu , Off. Hours: Lab Hours
Grader: Erdem Bala, 317 Evans, x1633, erdem _at_ udel.edu , Off. Hours: Lab Hours
Class Web-Site: http://www.ee.udel.edu/~blankenb/cpeg324
Laboratory Information:
133 Evans Hall – 16 SUN Workstations (Cadence/Synopsys tools run on these machines)
132 Evans Hall – 26 XP/Linux Workstations (remote login to SUN workstations)
140 DuPont Hall – 24 XP Workstations (remote login to SUN in 133)
Textbook: “Computer Organization & Design: The Hardware/Software Interface,” by David A. Patterson and John L. Hennessy (3rd edition, 2004) – to be used as general reference.
Course Description: Principles of computer system design are studied emphasizing tradeoffs involving cost, performance, testability, reliability and manufacturability. Topics include timing analysis, component and subsystem interconnect, noise effects debugging techniques, boundary scan testing and printed circuit layout. Laboratory work involves design and implementation of a computer subsystem.
In this course you will design and simulate a printed circuit daughter-board for XSA-50 prototyping board from XESS Corporation. Your board design will implement a custom gigabit serial link interface. Gigabit serial links are used PCI express, Serial ATA (SATA), USB 2.0, FIREWIRE, DVI, HDMI and other applications. In addition to designing your board, you will also develop a bill of materials (BOM) for manufacturing 100 boards. In the next course (CPEG 422: Computer Systems Design II), you will use a physical daughter-board to design, implement and test a real gigabit link.
Collaboration: For projects, you will team in groups of 2. Homework and tests are to be completed individually.
Design Tools: Cadence Allegro for printed circuit board design, Synopsys VHDL for system simulation and timing analysis.
Homework: 5%
Test 1: 15%
Test 2: 15%
Quiz: 15%
Project: 50%