CPEG324 Project: Gigabit Serial Interface Daughter-Board
XESS Corp. makes a popular FPGA prototyping board called the XSA-50 (see figure 1). We use XSA-50 boards in CPEG422 course (Computer Systems Design II) to implement digital designs synthesized from VHDL code. The project for this class is to design and simulate a daughter-board that attaches to the “bed-of-nails” connector on the back-side of XSA-50. The daughter-board implements a gigabit serial interface using DS92LV16 LVDS SERializer/DESerializer (SERDES) chip from National Semiconductor. The external I/O for the daughterboard consists of 4 SMA connectors implementing one differential gigabit LVDS input port and one differential gigabit LVDS output port (see figure 2). Using this daughterboard together four SMA cables enables one to implement a bidirectional gigabit link between two XSA-50 boards. That will be your hardware project in CPEG422, but we are running a bit ahead of ourselves.
In a nutshell, the SERDES chip takes 16 lanes of low-speed data (25 to 80MHz) and multiplexes them into a single gigabit data stream (see figure 3). In addition to 16 I/O data lanes, the SERDES chip includes a clock input and a number of low-speed inputs and outputs for low-speed control signals. The “bed-of-nails” connector on XSA-50 has connections for power, ground and low-speed I/O with the FPGA. The daughter-board connects FPGA I/O pins to the SERDES chip and also powers the SERDES chip through the “bed-of-nails” connector.
The project is divided into several parts:
Specify all the components (e.g. chips, resistors, capacitors, connectors) that will be used in your board design. Come up with printed circuit board specification (physical size and number of wiring layers). Implement a spreadsheet to calculate the BOM for manufacturing 100 boards (do not include the labor cost). Study the SERDES and XSA-50 datasheets and identify the I/O and power pins that need to be connected on the “bed-of-nails” connector.
Turn-in a write-up that includes a block diagram of your board design, a list of all the components you plan to use, a list of connections assignments for the “bed-of-nails” connector, and a BOM for manufacturing 100 boards.
Use Cadence Allegro CAD tool to design the pads and the physical footprints for the components in your design, which are not included in the standard footprint library that comes with Allegro. Create schematic symbols for these new footprints that map physical and logical pins. Turn in a write-up that documents the footprints and symbols that you have created.
Use Cadence Allegro CAD tool to design the schematic for your daughter-board. Turn in a write-up that documents the schematic design.
Use Cadence Allegro CAD tool to place all the components on the daughter-board. Then auto-route the low-speed signals and hand-route the gigabit signals. Turn in a write-up that documents the placed and routed board design that you have now completed.
Using the provided code template, write VHDL code for PLL Timing system of the SERDES chip. This code takes low-speed input clock and produces a gigabit clock used internally in the SERDES model. Turn in listing of your VHDL code with snapshot of timing waveform.
Using the provided code template, write VHDL code for SERDES Transmitter. Turn in listing of your VHDL code with snapshot of timing waveform.
Using the provided code template, write VHDL code for SERDES Receiver. Turn in listing of your VHDL code with snapshot of timing waveform.
Using the provided code template and your VHDL model of the SERDES chip, simulate a gigabit link between two daughter-boards. Turn in listing of your VHDL code with snapshot of timing waveform.
Total % for turning-in the project parts (there are 8 of them) 16%
Grade for oral poster presentation 17%
-Guidelines for Poster
-Evaluation form - Bring to class for your presentation
Example Presentations: EX1 EX2
Grade for final report 17%
-Guidelines for Report
-Evaluation form - Staple this to the poster form and bring with the report for the presentation session
Total (as % of your class grade) 50%
Note: Late submission automatically looses 50% of its grade.